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HAL_ChibiOS: fixed clock for FDCAN to be below 80MHz

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we were running at 100MHz, which is out of spec
This commit is contained in:
Andrew Tridgell 2020-04-24 09:32:23 +10:00
parent 2c68ce1986
commit db642717be
1 changed files with 4 additions and 4 deletions
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8
libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h
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@ -105,7 +105,7 @@
#define STM32_PLL2_DIVN_VALUE 25
#define STM32_PLL2_DIVP_VALUE 2
#define STM32_PLL2_DIVQ_VALUE 2
#define STM32_PLL2_DIVQ_VALUE 4
#define STM32_PLL2_DIVR_VALUE 2
#define STM32_PLL3_DIVN_VALUE 72
@ -179,10 +179,10 @@
#define STM32_QSPISEL STM32_QSPISEL_HCLK
#define STM32_FMCSEL STM32_QSPISEL_HCLK
#define STM32_SWPSEL STM32_SWPSEL_PCLK1
#define STM32_FDCANSEL STM32_FDCANSEL_PLL1_Q_CK
#define STM32_FDCANSEL STM32_FDCANSEL_PLL2_Q_CK
#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
#define STM32_SPI45SEL STM32_SPI45SEL_PLL2_Q_CK
#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2
#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK
#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK
#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
@ -193,7 +193,7 @@
#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
#define STM32_USART16SEL STM32_USART16SEL_PCLK2
#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1
#define STM32_SPI6SEL STM32_SPI6SEL_PLL2_Q_CK
#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4
#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
#define STM32_ADCSEL STM32_ADCSEL_PLL3_R_CK