HAL_ChibiOS: support no-crystal F3 setups
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@ -32,12 +32,30 @@
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_LSE_ENABLED FALSE
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#if STM32_HSECLK == 0U
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// use HSI, disable HSE
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSI
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#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
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#define STM32_PLLMUL_VALUE 16
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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// can't do more than 64MHz with HSI
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#undef HAL_EXPECTED_SYSCLOCK
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#define HAL_EXPECTED_SYSCLOCK 64000000
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#elif STM32_HSECLK == 8000000U
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#define STM32_HSI_ENABLED FALSE
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#define STM32_LSI_ENABLED FALSE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSE_ENABLED FALSE
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#if STM32_HSECLK == 8000000U
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
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@ -46,7 +64,11 @@
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_HPRE STM32_HPRE_DIV1
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#elif STM32_HSECLK == 24000000U
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#define STM32_HSI_ENABLED FALSE
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#define STM32_LSI_ENABLED FALSE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
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@ -60,7 +82,9 @@
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#endif
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#ifndef STM32_RTCSEL
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#define STM32_RTCSEL STM32_RTCSEL_HSEDIV
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#endif
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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