HAL_ChibiOS: reformat using yapf and support python3
allow hwdef.h compilation using python3
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@ -4,182 +4,194 @@ import sys, fnmatch
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import importlib
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import importlib
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# peripheral types that can be shared, wildcard patterns
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# peripheral types that can be shared, wildcard patterns
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SHARED_MAP = [ "I2C*", "USART*_TX", "UART*_TX", "SPI*" ]
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SHARED_MAP = ["I2C*", "USART*_TX", "UART*_TX", "SPI*"]
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ignore_list = []
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ignore_list = []
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dma_map = None
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dma_map = None
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debug = False
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debug = False
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def check_possibility(periph, dma_stream, curr_dict, dma_map, check_list):
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def check_possibility(periph, dma_stream, curr_dict, dma_map, check_list):
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for other_periph in curr_dict:
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for other_periph in curr_dict:
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if other_periph != periph:
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if other_periph != periph:
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if curr_dict[other_periph] == dma_stream:
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if curr_dict[other_periph] == dma_stream:
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ignore_list.append(periph)
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ignore_list.append(periph)
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check_str = "%s(%d,%d) %s(%d,%d)" % (
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check_str = "%s(%d,%d) %s(%d,%d)" % (
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other_periph,
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other_periph, curr_dict[other_periph][0],
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curr_dict[other_periph][0],
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curr_dict[other_periph][1], periph, dma_stream[0],
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curr_dict[other_periph][1],
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dma_stream[1])
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periph,
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#check if we did this before
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dma_stream[0],
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if check_str in check_list:
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dma_stream[1])
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return False
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#check if we did this before
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check_list.append(check_str)
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if check_str in check_list:
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if debug:
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return False
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print("Trying to Resolve Conflict: ", check_str)
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check_list.append(check_str)
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#check if we can resolve by swapping with other periphs
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if debug:
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for stream in dma_map[other_periph]:
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print("Trying to Resolve Conflict: ", check_str)
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if stream != curr_dict[other_periph] and \
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#check if we can resolve by swapping with other periphs
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check_possibility(other_periph, stream, curr_dict, dma_map, check_list):
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for stream in dma_map[other_periph]:
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curr_dict[other_periph] = stream
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if stream != curr_dict[other_periph] and \
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return True
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check_possibility(other_periph, stream, curr_dict, dma_map, check_list):
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return False
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curr_dict[other_periph] = stream
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return True
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return True
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return False
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return True
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def can_share(periph):
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def can_share(periph):
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'''check if a peripheral is in the SHARED_MAP list'''
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'''check if a peripheral is in the SHARED_MAP list'''
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for f in SHARED_MAP:
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for f in SHARED_MAP:
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if fnmatch.fnmatch(periph, f):
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if fnmatch.fnmatch(periph, f):
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return True
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return True
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if debug:
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if debug:
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print("%s can't share" % periph)
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print("%s can't share" % periph)
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return False
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return False
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def chibios_dma_define_name(key):
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def chibios_dma_define_name(key):
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'''return define name needed for board.h for ChibiOS'''
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'''return define name needed for board.h for ChibiOS'''
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if key.startswith('ADC'):
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if key.startswith('ADC'):
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return 'STM32_ADC_%s_DMA_STREAM' % key
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return 'STM32_ADC_%s_DMA_STREAM' % key
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elif key.startswith('SPI'):
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elif key.startswith('SPI'):
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return 'STM32_SPI_%s_DMA_STREAM' % key
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return 'STM32_SPI_%s_DMA_STREAM' % key
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elif key.startswith('I2C'):
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elif key.startswith('I2C'):
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return 'STM32_I2C_%s_DMA_STREAM' % key
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return 'STM32_I2C_%s_DMA_STREAM' % key
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elif key.startswith('USART'):
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elif key.startswith('USART'):
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return 'STM32_UART_%s_DMA_STREAM' % key
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return 'STM32_UART_%s_DMA_STREAM' % key
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elif key.startswith('UART'):
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elif key.startswith('UART'):
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return 'STM32_UART_%s_DMA_STREAM' % key
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return 'STM32_UART_%s_DMA_STREAM' % key
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elif key.startswith('SDIO'):
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elif key.startswith('SDIO'):
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return 'STM32_SDC_%s_DMA_STREAM' % key
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return 'STM32_SDC_%s_DMA_STREAM' % key
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elif key.startswith('TIM'):
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elif key.startswith('TIM'):
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return 'STM32_RCIN_DMA_STREAM'
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return 'STM32_RCIN_DMA_STREAM'
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else:
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else:
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print("Error: Unknown key type %s" % key)
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print("Error: Unknown key type %s" % key)
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sys.exit(1)
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sys.exit(1)
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def write_dma_header(f, peripheral_list, mcu_type):
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def write_dma_header(f, peripheral_list, mcu_type):
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'''write out a DMA resolver header file'''
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'''write out a DMA resolver header file'''
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global dma_map
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global dma_map
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try:
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try:
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lib = importlib.import_module(mcu_type)
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lib = importlib.import_module(mcu_type)
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dma_map = lib.DMA_Map
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dma_map = lib.DMA_Map
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except ImportError:
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except ImportError:
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print("Unable to find module for MCU %s" % mcu_type)
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print("Unable to find module for MCU %s" % mcu_type)
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sys.exit(1)
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sys.exit(1)
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print("Writing DMA map")
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unassigned = []
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curr_dict = {}
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for periph in peripheral_list:
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print("Writing DMA map")
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assigned = False
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unassigned = []
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check_list = []
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curr_dict = {}
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if not periph in dma_map:
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print("Unknown peripheral function %s in DMA map for %s" % (periph, mcu_type))
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sys.exit(1)
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for stream in dma_map[periph]:
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if check_possibility(periph, stream, curr_dict, dma_map, check_list):
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curr_dict[periph] = stream
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assigned = True
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break
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if assigned == False:
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unassigned.append(periph)
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# now look for shared DMA possibilities
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for periph in peripheral_list:
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stream_assign = {}
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assigned = False
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for k in curr_dict.iterkeys():
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check_list = []
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stream_assign[curr_dict[k]] = [k]
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if not periph in dma_map:
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print("Unknown peripheral function %s in DMA map for %s" %
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(periph, mcu_type))
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sys.exit(1)
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for stream in dma_map[periph]:
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if check_possibility(periph, stream, curr_dict, dma_map,
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check_list):
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curr_dict[periph] = stream
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assigned = True
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break
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if assigned == False:
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unassigned.append(periph)
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unassigned_new = unassigned[:]
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# now look for shared DMA possibilities
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for periph in unassigned:
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stream_assign = {}
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for stream in dma_map[periph]:
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for k in curr_dict.keys():
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share_ok = True
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stream_assign[curr_dict[k]] = [k]
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for periph2 in stream_assign[stream]:
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if not can_share(periph) or not can_share(periph2):
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share_ok = False
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if share_ok:
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if debug:
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print("Sharing %s on %s with %s" % (periph, stream, stream_assign[stream]))
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curr_dict[periph] = stream
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stream_assign[stream].append(periph)
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unassigned_new.remove(periph)
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break
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unassigned = unassigned_new
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unassigned_new = unassigned[:]
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for periph in unassigned:
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for stream in dma_map[periph]:
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share_ok = True
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for periph2 in stream_assign[stream]:
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if not can_share(periph) or not can_share(periph2):
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share_ok = False
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if share_ok:
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if debug:
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print("Sharing %s on %s with %s" % (periph, stream,
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stream_assign[stream]))
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curr_dict[periph] = stream
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stream_assign[stream].append(periph)
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unassigned_new.remove(periph)
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break
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unassigned = unassigned_new
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f.write("// auto-generated DMA mapping from dma_resolver.py\n")
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f.write("// auto-generated DMA mapping from dma_resolver.py\n")
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if unassigned:
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if unassigned:
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f.write("\n// Note: The following peripherals can't be resolved for DMA: %s\n\n" % unassigned)
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f.write(
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"\n// Note: The following peripherals can't be resolved for DMA: %s\n\n"
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% unassigned)
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for key in sorted(curr_dict.iterkeys()):
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for key in sorted(curr_dict.keys()):
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stream = curr_dict[key]
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stream = curr_dict[key]
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shared = ''
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shared = ''
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if len(stream_assign[stream]) > 1:
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if len(stream_assign[stream]) > 1:
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shared = ' // shared %s' % ','.join(stream_assign[stream])
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shared = ' // shared %s' % ','.join(stream_assign[stream])
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f.write("#define %-30s STM32_DMA_STREAM_ID(%u, %u)%s\n" % (chibios_dma_define_name(key),
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f.write("#define %-30s STM32_DMA_STREAM_ID(%u, %u)%s\n" %
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curr_dict[key][0],
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(chibios_dma_define_name(key), curr_dict[key][0],
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curr_dict[key][1],
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curr_dict[key][1], shared))
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shared))
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# now generate UARTDriver.cpp DMA config lines
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f.write("\n\n// generated UART DMA configuration lines\n")
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for u in range(1,9):
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key = None
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if 'USART%u_TX' % u in peripheral_list:
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key = 'USART%u' % u
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if 'UART%u_TX' % u in peripheral_list:
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key = 'UART%u' % u
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if 'USART%u_RX' % u in peripheral_list:
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key = 'USART%u' % u
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if 'UART%u_RX' % u in peripheral_list:
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key = 'UART%u' % u
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if key is None:
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continue
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f.write("#define STM32_%s_RX_DMA_CONFIG " % key)
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if key + "_RX" in curr_dict:
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f.write("true, STM32_UART_%s_RX_DMA_STREAM, STM32_%s_RX_DMA_CHN\n" % (key, key))
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else:
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f.write("false, 0, 0\n")
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f.write("#define STM32_%s_TX_DMA_CONFIG " % key)
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if key + "_TX" in curr_dict:
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f.write("true, STM32_UART_%s_TX_DMA_STREAM, STM32_%s_TX_DMA_CHN\n" % (key, key))
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else:
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f.write("false, 0, 0\n")
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# now generate UARTDriver.cpp DMA config lines
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f.write("\n\n// generated UART DMA configuration lines\n")
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for u in range(1, 9):
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key = None
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if 'USART%u_TX' % u in peripheral_list:
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key = 'USART%u' % u
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if 'UART%u_TX' % u in peripheral_list:
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key = 'UART%u' % u
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if 'USART%u_RX' % u in peripheral_list:
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key = 'USART%u' % u
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if 'UART%u_RX' % u in peripheral_list:
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key = 'UART%u' % u
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if key is None:
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continue
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f.write("#define STM32_%s_RX_DMA_CONFIG " % key)
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if key + "_RX" in curr_dict:
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f.write(
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"true, STM32_UART_%s_RX_DMA_STREAM, STM32_%s_RX_DMA_CHN\n" %
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(key, key))
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else:
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f.write("false, 0, 0\n")
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f.write("#define STM32_%s_TX_DMA_CONFIG " % key)
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if key + "_TX" in curr_dict:
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f.write(
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"true, STM32_UART_%s_TX_DMA_STREAM, STM32_%s_TX_DMA_CHN\n" %
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(key, key))
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else:
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f.write("false, 0, 0\n")
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if __name__ == '__main__':
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if __name__ == '__main__':
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import optparse
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import optparse
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parser = optparse.OptionParser("dma_resolver.py")
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parser = optparse.OptionParser("dma_resolver.py")
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parser.add_option("-M", "--mcu", default=None, help='MCU type')
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parser.add_option("-M", "--mcu", default=None, help='MCU type')
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parser.add_option("-D", "--debug", action='store_true', help='enable debug')
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parser.add_option(
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parser.add_option("-P", "--peripherals", default=None, help='peripheral list (comma separated)')
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"-D", "--debug", action='store_true', help='enable debug')
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parser.add_option(
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"-P",
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"--peripherals",
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default=None,
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help='peripheral list (comma separated)')
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opts, args = parser.parse_args()
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opts, args = parser.parse_args()
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if opts.peripherals is None:
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if opts.peripherals is None:
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print("Please provide a peripheral list with -P")
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print("Please provide a peripheral list with -P")
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sys.exit(1)
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sys.exit(1)
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if opts.mcu is None:
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if opts.mcu is None:
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print("Please provide a MCU type with -<")
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print("Please provide a MCU type with -<")
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sys.exit(1)
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sys.exit(1)
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debug = opts.debug
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debug = opts.debug
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plist = opts.peripherals.split(',')
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plist = opts.peripherals.split(',')
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mcu_type = opts.mcu
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mcu_type = opts.mcu
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f = open("dma.h", "w")
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f = open("dma.h", "w")
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write_dma_header(f, plist, mcu_type)
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write_dma_header(f, plist, mcu_type)
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