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AP_HAL_ChibiOS: add alt config GPIO to Matek F765-Wing

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Based on new functionality introduced in #18753
This commit is contained in:
kniuk 2021-10-08 03:19:08 +02:00 committed by Andrew Tridgell
parent bc7c5c24da
commit aabb6f7c59
1 changed files with 13 additions and 1 deletions
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14
libraries/AP_HAL_ChibiOS/hwdef/MatekF765-Wing/hwdef.dat
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@ -119,10 +119,11 @@ PB8 UART5_RX UART5 NODMA
PC7 TIM3_CH2 TIM3 RCININT PULLDOWN LOW PC7 TIM3_CH2 TIM3 RCININT PULLDOWN LOW
PC6 USART6_TX USART6 NODMA PC6 USART6_TX USART6 NODMA
# as an alternative config setup the RX6 pin as a uart. This allows # as an alternative config setup the RX6 pin as an uart. This allows
# for bi-directional UART based receiver protocols such as FPort # for bi-directional UART based receiver protocols such as FPort
# without any extra hardware # without any extra hardware
PC7 USART6_RX USART6 NODMA ALT(1) PC7 USART6_RX USART6 NODMA ALT(1)
PC7 USART6_RX USART6 NODMA ALT(3)
# UART7 (telem1) # UART7 (telem1)
PE7 UART7_RX UART7 PE7 UART7_RX UART7
@ -130,6 +131,17 @@ PE8 UART7_TX UART7
PE10 UART7_CTS UART7 PE10 UART7_CTS UART7
PE9 UART7_RTS UART7 PE9 UART7_RTS UART7
# telem1-UART7 RTS and CTS as GPIO in alternative configs
PE10 EXTERN_GPIO1 OUTPUT GPIO(1) ALT(2) # Cts7 pin as GPIO 1 (set RELAY_PINx = 1 to use it)
PE9 EXTERN_GPIO2 OUTPUT GPIO(2) ALT(2) # Rts7 pin as GPIO 2 (set RELAY_PINx = 2 to use it)
PE10 EXTERN_GPIO1 OUTPUT GPIO(1) ALT(3) # Cts7 pin as GPIO 1 (set RELAY_PINx = 1 to use it)
PE9 EXTERN_GPIO2 OUTPUT GPIO(2) ALT(3) # Rts7 pin as GPIO 2 (set RELAY_PINx = 2 to use it)
# alternative configs:
# 1: bidirectional receiver protocol on RX6 pin
# 2: extra GPIOs instead of Cts/Rts on UART7_CTS
# 3: both 1 and 2 combined, GPIO numbers differ to avoid "Duplicate GPIO value" error while generating hwdef.h
# UART8 (spare) # UART8 (spare)
PE0 UART8_RX UART8 NODMA PE0 UART8_RX UART8 NODMA
PE1 UART8_TX UART8 NODMA PE1 UART8_TX UART8 NODMA