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AP_HAL_ChibiOS: pull RTS lines low on Pixhawk6C to avoid glitches on startup

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Andy Piper 2023-06-29 19:37:45 +01:00 committed by Andrew Tridgell
parent ee0f3c5f51
commit 87a405152f
1 changed files with 6 additions and 5 deletions
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11
libraries/AP_HAL_ChibiOS/hwdef/Pixhawk6C/hwdef.dat
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@ -1,6 +1,10 @@
# hw definition file for processing by chibios_hwdef.py # hw definition file for processing by chibios_hwdef.py
# for the HolybroV6C hardware # for the HolybroV6C hardware
# default to all pins low to avoid ESD issues
#DEFAULTGPIO OUTPUT LOW PULLDOWN
# MCU class and specific type # MCU class and specific type
MCU STM32H7xx STM32H743xx MCU STM32H7xx STM32H743xx
@ -35,9 +39,6 @@ SERIAL_ORDER OTG1 UART7 UART5 USART1 UART8 USART2 USART3 OTG2
# default the 2nd interface to MAVLink2 # default the 2nd interface to MAVLink2
define HAL_OTG2_PROTOCOL SerialProtocol_MAVLink2 define HAL_OTG2_PROTOCOL SerialProtocol_MAVLink2
# default to all pins low to avoid ESD issues
DEFAULTGPIO OUTPUT LOW PULLDOWN
# USB # USB
PA11 OTG_FS_DM OTG1 PA11 OTG_FS_DM OTG1
PA12 OTG_FS_DP OTG1 PA12 OTG_FS_DP OTG1
@ -50,13 +51,13 @@ PA14 JTCK-SWCLK SWD
# telem1 # telem1
PE8 UART7_TX UART7 PE8 UART7_TX UART7
PE7 UART7_RX UART7 PE7 UART7_RX UART7
PE9 UART7_RTS UART7 PE9 UART7_RTS UART7 LOW PULLDOWN
PE10 UART7_CTS UART7 PE10 UART7_CTS UART7
# telem2 # telem2
PC12 UART5_TX UART5 PC12 UART5_TX UART5
PD2 UART5_RX UART5 PD2 UART5_RX UART5
PC8 UART5_RTS UART5 PC8 UART5_RTS UART5 LOW PULLDOWN
PC9 UART5_CTS UART5 PC9 UART5_CTS UART5
# GPS1 # GPS1