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HAL_ChibiOS: removed ID_ANY streams for H7

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use generated map instead
This commit is contained in:
Andrew Tridgell 2019-02-14 21:19:07 +11:00
parent ee1d2e8edb
commit 77d4e1f796
1 changed files with 4 additions and 31 deletions
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35
libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h
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@ -230,8 +230,6 @@
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC12 TRUE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
@ -239,6 +237,10 @@
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
// we call it ADC1 in hwdef.dat, but driver uses ADC12 for DMA stream
#define STM32_ADC_ADC12_DMA_STREAM STM32_ADC_ADC1_DMA_STREAM
/*
* CAN driver system settings.
*/
@ -259,8 +261,6 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -294,14 +294,6 @@
* I2C driver system settings.
*/
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -367,7 +359,6 @@
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
@ -413,8 +404,6 @@
#ifndef STM32_SPI_USE_SPI6
#define STM32_SPI_USE_SPI6 FALSE
#endif
#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -440,22 +429,6 @@
/*
* UART driver system settings.
*/
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12