AP_HAL_ChibiOS: add support for marking ADC pins with identifier
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@ -2191,7 +2191,7 @@ def write_ADC_config(f):
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'''write ADC config defines'''
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f.write('// ADC config\n')
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adc_chans = [[], [], []]
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index = 0
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analogset = {252, 253, 254} # reserved values for VSENSE, VREF and VBAT in H7
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for l in bylabel:
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p = bylabel[l]
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if not p.type.startswith('ADC'):
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@ -2208,45 +2208,79 @@ def write_ADC_config(f):
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else:
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raise ValueError("Unknown ADC type %s" % p.type)
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scale = p.extra_value('SCALE', default=None)
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analog = p.extra_value('ANALOG', type=int, default=chan) # default to ADC channel if not specified
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if analog in analogset:
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error("Duplicate analog pin %u" % analog)
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analogset.add(analog)
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if p.label == 'VDD_5V_SENS':
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f.write('#define ANALOG_VCC_5V_PIN %u\n' % (chan + index*20))
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f.write('#define ANALOG_VCC_5V_PIN %u\n' % (analog))
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f.write('#define HAL_HAVE_BOARD_VOLTAGE 1\n')
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if p.label == 'FMU_SERVORAIL_VCC_SENS':
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f.write('#define FMU_SERVORAIL_ADC_CHAN %u\n' % (chan + index*20))
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f.write('#define FMU_SERVORAIL_ADC_PIN %u\n' % (analog))
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f.write('#define HAL_HAVE_SERVO_VOLTAGE 1\n')
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adc_chans[index].append((chan, scale, p.label, p.portpin))
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adc_chans[index] = sorted(adc_chans[index])
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adc_chans[index].append((chan, analog, scale, p.label, p.portpin))
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# sort by ADC channel
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for index in range(3):
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adc_chans[index] = sorted(adc_chans[index])
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if len(adc_chans[1]) > 0:
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# ensure ADC1 and ADC2 are of same size
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if len(adc_chans[0]) > len(adc_chans[1]):
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# add dummy channel that's not already in adc_chans[1]
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for chan in range(1,19):
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if chan not in [c[0] for c in adc_chans[1]]:
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adc_chans[1].append((chan, 255, None, 'dummy', 'dummy'))
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break
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elif len(adc_chans[0]) < len(adc_chans[1]):
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# add dummy channel that's not already in adc_chans[0]
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for chan in range(1,19):
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if chan not in [c[0] for c in adc_chans[0]]:
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adc_chans[0].append((chan, 255, None, 'dummy', 'dummy'))
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break
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# check if ADC1 and ADC2 list if they have the same channel for same index
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# if not then jumble the channels around to have no matching channels
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for i in range(len(adc_chans[0])):
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if adc_chans[0][i][0] == adc_chans[1][i][0]:
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# found a match, jumble the channels around
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for j in range(len(adc_chans[0])):
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if adc_chans[0][j][0] != adc_chans[1][j][0]:
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# found a non-match, swap the channels
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adc_chans[0][i], adc_chans[0][j] = adc_chans[0][j], adc_chans[0][i]
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break
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vdd = get_config('STM32_VDD', default='330U')
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if vdd[-1] == 'U':
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vdd = vdd[:-1]
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vdd = float(vdd) * 0.01
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f.write('#define HAL_ANALOG_PINS \\\n')
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for (chan, scale, label, portpin) in adc_chans[0]:
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for (chan, analog, scale, label, portpin) in adc_chans[0]:
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scale_str = '%.2f/4096' % vdd
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if scale is not None and scale != '1':
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scale_str = scale + '*' + scale_str
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f.write('{ %2u, %12s }, /* %s %s */ \\\n' % (chan, scale_str, portpin,
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f.write('{ %2u, %2u, %12s }, /* %s %s */ \\\n' % (chan, analog, scale_str, portpin,
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label))
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f.write('\n\n')
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if len(adc_chans[1]) > 0:
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f.write('#define STM32_ADC_SAMPLES_SIZE 32\n')
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f.write('#define ADC12_CCR_DUAL ADC_CCR_DUAL_REG_INTERL\n')
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f.write('#define STM32_ADC_DUAL_MODE TRUE\n')
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f.write('#define HAL_ANALOG2_PINS \\\n')
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for (chan, scale, label, portpin) in adc_chans[1]:
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for (chan, analog, scale, label, portpin) in adc_chans[1]:
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scale_str = '%.2f/4096' % vdd
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if scale is not None and scale != '1':
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scale_str = scale + '*' + scale_str
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f.write('{ %2u, %12s }, /* %s %s */ \\\n' % (chan, scale_str, portpin,
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f.write('{ %2u, %2u, %12s }, /* %s %s */ \\\n' % (chan, analog, scale_str, portpin,
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label))
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f.write('\n\n')
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if len(adc_chans[2]) > 0:
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f.write('#define STM32_ADC_USE_ADC3 TRUE\n')
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f.write('#define HAL_ANALOG3_PINS \\\n')
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for (chan, scale, label, portpin) in adc_chans[2]:
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for (chan, analog, scale, label, portpin) in adc_chans[2]:
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scale_str = '%.2f/4096' % vdd
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if scale is not None and scale != '1':
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scale_str = scale + '*' + scale_str
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f.write('{ %2u, %12s }, /* %s %s */ \\\n' % (chan, scale_str, portpin,
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f.write('{ %2u, %2u, %12s }, /* %s %s */ \\\n' % (chan, analog, scale_str, portpin,
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label))
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f.write('\n\n')
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