From 29f538dec9842727a229752606d35a1e3fbef804 Mon Sep 17 00:00:00 2001
From: Andrew Tridgell <andrew@tridgell.net>
Date: Fri, 24 Apr 2020 13:22:00 +1000
Subject: [PATCH] HAL_ChibiOS: use common header for STM32 clock config

avoid the need for clock config lines in most hwdef.dat files
---
 .../hwdef/common/stm32f47_mcuconf.h           | 48 ++++++++++++++++++-
 1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/libraries/AP_HAL_ChibiOS/hwdef/common/stm32f47_mcuconf.h b/libraries/AP_HAL_ChibiOS/hwdef/common/stm32f47_mcuconf.h
index 015b3856a4..31434196bb 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/common/stm32f47_mcuconf.h
+++ b/libraries/AP_HAL_ChibiOS/hwdef/common/stm32f47_mcuconf.h
@@ -81,9 +81,55 @@
 #ifndef STM32_PLLSRC
 #define STM32_PLLSRC                        STM32_PLLSRC_HSE
 #endif
-#ifndef STM32_PLLM_VALUE
+
+#if !defined(HAL_CUSTOM_CLOCK_TREE)
+#if defined(STM32F7xx_MCUCONF)
+// F7 clock config
+#if STM32_HSECLK == 8000000U
+#define STM32_PLLM_VALUE                    8
+#define STM32_PLLN_VALUE                    432
+#define STM32_PLLP_VALUE                    2
+#define STM32_PLLQ_VALUE                    9
+#elif STM32_HSECLK == 16000000U
+#define STM32_PLLM_VALUE                    8
+#define STM32_PLLN_VALUE                    216
+#define STM32_PLLP_VALUE                    2
+#define STM32_PLLQ_VALUE                    9
+#elif STM32_HSECLK == 24000000U
 #define STM32_PLLM_VALUE                    24
+#define STM32_PLLN_VALUE                    432
+#define STM32_PLLP_VALUE                    2
+#define STM32_PLLQ_VALUE                    9
+#else
+#error "Unsupported F7 HSE clock"
 #endif
+#else // F4
+// F4 clock config
+#if STM32_HSECLK == 8000000U
+#define STM32_PLLM_VALUE                    8
+#define STM32_PLLN_VALUE                    336
+#define STM32_PLLP_VALUE                    2
+#define STM32_PLLQ_VALUE                    7
+#elif STM32_HSECLK == 16000000U
+#define STM32_PLLM_VALUE                    16
+#define STM32_PLLN_VALUE                    384
+#define STM32_PLLP_VALUE                    4
+#define STM32_PLLQ_VALUE                    8
+#elif STM32_HSECLK == 24000000U
+#define STM32_PLLM_VALUE                    24
+#define STM32_PLLN_VALUE                    336
+#define STM32_PLLP_VALUE                    2
+#define STM32_PLLQ_VALUE                    7
+#else
+#error "Unsupported F4 HSE clock"
+#endif
+#endif // MCU
+#endif // HAL_CUSTOM_CLOCK_TREE
+
+// we don't use LSE, but we need the defines
+#define STM32_LSECLK   32768U
+#define STM32_LSEDRV   (3U << 3U)
+
 #ifndef STM32_PLLN_VALUE
 #define STM32_PLLN_VALUE                    336
 #endif