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AP_HAL_ChibiOS: H7 set SRAM4 to no cache and allow DMA

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Iampete1 2021-04-01 13:49:21 +01:00 committed by Andrew Tridgell
parent b369e86c0c
commit 2377d33417
2 changed files with 10 additions and 1 deletions
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9
libraries/AP_HAL_ChibiOS/hwdef/common/board.c
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@ -235,6 +235,15 @@ void __early_init(void) {
#if defined(HAL_DISABLE_DCACHE) #if defined(HAL_DISABLE_DCACHE)
SCB_DisableDCache(); SCB_DisableDCache();
#endif #endif
#if defined(STM32H7)
// disable cache on SRAM4 so we can use it for DMA
mpuConfigureRegion(MPU_REGION_5,
0x38000000U,
MPU_RASR_ATTR_AP_RW_RW |
MPU_RASR_ATTR_NON_CACHEABLE |
MPU_RASR_SIZE_64K |
MPU_RASR_ENABLE);
#endif
} }
void __late_init(void) { void __late_init(void) {

2
libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py
View File

@ -21,9 +21,9 @@ mcu = {
'RAM_MAP' : [ 'RAM_MAP' : [
(0x20000000, 128, 2), # DTCM, tightly coupled, no DMA, fast (0x20000000, 128, 2), # DTCM, tightly coupled, no DMA, fast
(0x30000000, 256, 0), # SRAM1, SRAM2 (0x30000000, 256, 0), # SRAM1, SRAM2
(0x38000000, 64, 0), # SRAM4.
(0x24000000, 512, 4), # AXI SRAM. Use this for SDMMC IDMA ops (0x24000000, 512, 4), # AXI SRAM. Use this for SDMMC IDMA ops
(0x00000400, 63, 2), # ITCM (first 1k removed, to keep address 0 unused) (0x00000400, 63, 2), # ITCM (first 1k removed, to keep address 0 unused)
(0x38000000, 64, 1), # SRAM4.
(0x30040000, 32, 1), # SRAM3. This supports both DMA and BDMA ops. (0x30040000, 32, 1), # SRAM3. This supports both DMA and BDMA ops.
], ],