From 2377d3341795bba4664d964fdc643f765b02ea08 Mon Sep 17 00:00:00 2001
From: Iampete1 <iampete@hotmail.co.uk>
Date: Thu, 1 Apr 2021 13:49:21 +0100
Subject: [PATCH] AP_HAL_ChibiOS: H7 set SRAM4 to no cache and allow DMA

---
 libraries/AP_HAL_ChibiOS/hwdef/common/board.c         | 9 +++++++++
 libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/libraries/AP_HAL_ChibiOS/hwdef/common/board.c b/libraries/AP_HAL_ChibiOS/hwdef/common/board.c
index 0f9a636dc0..11f64505a7 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/common/board.c
+++ b/libraries/AP_HAL_ChibiOS/hwdef/common/board.c
@@ -235,6 +235,15 @@ void __early_init(void) {
 #if defined(HAL_DISABLE_DCACHE)
   SCB_DisableDCache();
 #endif
+#if defined(STM32H7)
+  // disable cache on SRAM4 so we can use it for DMA
+  mpuConfigureRegion(MPU_REGION_5,
+                     0x38000000U,
+                     MPU_RASR_ATTR_AP_RW_RW |
+                     MPU_RASR_ATTR_NON_CACHEABLE |
+                     MPU_RASR_SIZE_64K |
+                     MPU_RASR_ENABLE);
+#endif
 }
 
 void __late_init(void) {
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py b/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py
index 55d85cd2fc..2ca777881d 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py
+++ b/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py
@@ -21,9 +21,9 @@ mcu = {
     'RAM_MAP' : [
         (0x20000000, 128, 2), # DTCM, tightly coupled, no DMA, fast
         (0x30000000, 256, 0), # SRAM1, SRAM2
-        (0x38000000,  64, 0), # SRAM4.
         (0x24000000, 512, 4), # AXI SRAM. Use this for SDMMC IDMA ops
         (0x00000400,  63, 2), # ITCM (first 1k removed, to keep address 0 unused)
+        (0x38000000,  64, 1), # SRAM4.
         (0x30040000,  32, 1), # SRAM3. This supports both DMA and BDMA ops.
     ],