HAL_ChibiOS: support mavcan message forwarding
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@ -378,7 +378,8 @@ int16_t CANIface::send(const AP_HAL::CANFrame& frame, uint64_t tx_deadline,
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pending_tx_[index].aborted = false;
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pending_tx_[index].setup = true;
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pending_tx_[index].pushed = false;
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return 1;
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return AP_HAL::CANIface::send(frame, tx_deadline, flags);
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}
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int16_t CANIface::receive(AP_HAL::CANFrame& out_frame, uint64_t& out_timestamp_us, CanIOFlags& out_flags)
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@ -391,7 +392,8 @@ int16_t CANIface::receive(AP_HAL::CANFrame& out_frame, uint64_t& out_timestamp_u
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out_frame = rx_item.frame;
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out_timestamp_us = rx_item.timestamp_us;
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out_flags = rx_item.flags;
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return 1;
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return AP_HAL::CANIface::receive(out_frame, out_timestamp_us, out_flags);
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}
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bool CANIface::configureFilters(const CanFilterConfig* filter_configs,
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@ -761,7 +763,7 @@ void CANIface::handleTxCompleteInterrupt(const uint64_t timestamp_us)
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rx_item.frame = pending_tx_[i].frame;
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rx_item.timestamp_us = timestamp_us;
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rx_item.flags = AP_HAL::CANIface::Loopback;
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rx_queue_.push(rx_item);
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add_to_rx_queue(rx_item);
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}
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if (event_handle_ != nullptr) {
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stats.num_events++;
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@ -855,7 +857,7 @@ bool CANIface::readRxFIFO(uint8_t fifo_index)
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rx_item.frame = frame;
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rx_item.timestamp_us = timestamp_us;
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rx_item.flags = 0;
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if (rx_queue_.push(rx_item)) {
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if (add_to_rx_queue(rx_item)) {
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stats.rx_received++;
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} else {
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stats.rx_overflow++;
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@ -240,6 +240,15 @@ public:
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// CAN Peripheral register structure, pointing at base
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// register. Indexed by locical interface number
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static constexpr CanType* const Can[HAL_NUM_CAN_IFACES] = { HAL_CAN_BASE_LIST };
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protected:
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bool add_to_rx_queue(const CanRxItem &rx_item) override {
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return rx_queue_.push(rx_item);
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}
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int8_t get_iface_num(void) const override {
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return self_index_;
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}
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};
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@ -238,6 +238,15 @@ public:
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// CAN Peripheral register structure
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static constexpr bxcan::CanType* const Can[HAL_NUM_CAN_IFACES] = { HAL_CAN_BASE_LIST };
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protected:
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bool add_to_rx_queue(const CanRxItem &rx_item) override {
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return rx_queue_.push(rx_item);
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}
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int8_t get_iface_num(void) const override {
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return self_index_;
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}
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};
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#endif //HAL_NUM_CAN_IFACES
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#endif //# if defined(STM32H7XX) || defined(STM32G4)
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@ -362,7 +362,8 @@ int16_t CANIface::send(const AP_HAL::CANFrame& frame, uint64_t tx_deadline,
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txi.abort_on_error = (flags & AbortOnError) != 0;
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// setup frame initial state
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txi.pushed = false;
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return 1;
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return AP_HAL::CANIface::send(frame, tx_deadline, flags);
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}
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int16_t CANIface::receive(AP_HAL::CANFrame& out_frame, uint64_t& out_timestamp_us, CanIOFlags& out_flags)
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@ -375,7 +376,8 @@ int16_t CANIface::receive(AP_HAL::CANFrame& out_frame, uint64_t& out_timestamp_u
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out_frame = rx_item.frame;
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out_timestamp_us = rx_item.timestamp_us;
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out_flags = rx_item.flags;
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return 1;
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return AP_HAL::CANIface::receive(out_frame, out_timestamp_us, out_flags);
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}
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#if !defined(HAL_BOOTLOADER_BUILD)
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@ -481,7 +483,7 @@ void CANIface::handleTxMailboxInterrupt(uint8_t mailbox_index, bool txok, const
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rx_item.timestamp_us = timestamp_us;
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rx_item.flags = AP_HAL::CANIface::Loopback;
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PERF_STATS(stats.tx_loopback);
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rx_queue_.push(rx_item);
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add_to_rx_queue(rx_item);
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}
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if (txok && !txi.pushed) {
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@ -569,7 +571,7 @@ void CANIface::handleRxInterrupt(uint8_t fifo_index, uint64_t timestamp_us)
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rx_item.frame = frame;
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rx_item.timestamp_us = timestamp_us;
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rx_item.flags = 0;
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if (rx_queue_.push(rx_item)) {
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if (add_to_rx_queue(rx_item)) {
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PERF_STATS(stats.rx_received);
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} else {
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PERF_STATS(stats.rx_overflow);
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