mirror of
https://github.com/ArduPilot/ardupilot
synced 2025-01-19 23:28:32 -04:00
104 lines
3.0 KiB
C
104 lines
3.0 KiB
C
/*
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* This file is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "stm32_util.h"
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <stm32_dma.h>
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/*
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setup the timer capture digital filter for a channel
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*/
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void stm32_timer_set_input_filter(stm32_tim_t *tim, uint8_t channel, uint8_t filter_mode)
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{
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switch (channel) {
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case 0:
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tim->CCMR1 |= STM32_TIM_CCMR1_IC1F(filter_mode);
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break;
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case 1:
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tim->CCMR1 |= STM32_TIM_CCMR1_IC2F(filter_mode);
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break;
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case 2:
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tim->CCMR2 |= STM32_TIM_CCMR2_IC3F(filter_mode);
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break;
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case 3:
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tim->CCMR2 |= STM32_TIM_CCMR2_IC4F(filter_mode);
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break;
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}
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}
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/*
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set the input source of a timer channel
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*/
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void stm32_timer_set_channel_input(stm32_tim_t *tim, uint8_t channel, uint8_t input_source)
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{
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switch (channel) {
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case 0:
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tim->CCER &= ~STM32_TIM_CCER_CC1E;
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tim->CCMR1 &= ~STM32_TIM_CCMR1_CC1S_MASK;
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tim->CCMR1 |= STM32_TIM_CCMR1_CC1S(input_source);
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tim->CCER |= STM32_TIM_CCER_CC1E;
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break;
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case 1:
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tim->CCER &= ~STM32_TIM_CCER_CC2E;
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tim->CCMR1 &= ~STM32_TIM_CCMR1_CC2S_MASK;
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tim->CCMR1 |= STM32_TIM_CCMR1_CC2S(input_source);
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tim->CCER |= STM32_TIM_CCER_CC2E;
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break;
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case 2:
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tim->CCER &= ~STM32_TIM_CCER_CC3E;
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tim->CCMR2 &= ~STM32_TIM_CCMR2_CC3S_MASK;
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tim->CCMR2 |= STM32_TIM_CCMR2_CC3S(input_source);
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tim->CCER |= STM32_TIM_CCER_CC3E;
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break;
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case 3:
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tim->CCER &= ~STM32_TIM_CCER_CC4E;
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tim->CCMR2 &= ~STM32_TIM_CCMR2_CC4S_MASK;
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tim->CCMR2 |= STM32_TIM_CCMR2_CC4S(input_source);
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tim->CCER |= STM32_TIM_CCER_CC4E;
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break;
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}
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}
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#if CH_DBG_ENABLE_STACK_CHECK == TRUE
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void show_stack_usage(void)
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{
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thread_t *tp;
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tp = chRegFirstThread();
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do {
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uint32_t stklimit = (uint32_t)tp->wabase;
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uint8_t *p = (uint8_t *)tp->wabase;
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while (*p == CH_DBG_STACK_FILL_VALUE) {
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p++;
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}
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uint32_t stack_left = ((uint32_t)p) - stklimit;
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printf("%s %u\n", tp->name, (unsigned)stack_left);
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tp = chRegNextThread(tp);
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} while (tp != NULL);
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}
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#endif
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/*
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flush all memory. Used in chSysHalt()
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*/
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void memory_flush_all(void)
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{
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#if defined(STM32F7) && STM32_DMA_CACHE_HANDLING == TRUE
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dmaBufferFlush(HAL_RAM_BASE_ADDRESS, HAL_RAM_SIZE_KB * 1024U);
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#endif
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}
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