mirror of
https://github.com/ArduPilot/ardupilot
synced 2025-01-07 16:38:30 -04:00
667b386356
convert RCOutput to new virtual timer interface cope with SDC vs SDMMC use new SPIv3 driver. Correct clocks for SDMMCv2. add STM32L431 support port ChibiOS config to version 8 support SPIv3 driver model v2 on H7 use currcore in debug options use new mmc API disable speed optimizations in the bootloader to save a little flash upgrade to halconf v8.4 relax constraints on QSP/flash clock. add support for disabling QSPI reset in main firmware
476 lines
14 KiB
C++
476 lines
14 KiB
C++
/*
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* This file is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <hal.h>
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#include "I2CDevice.h"
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#include <AP_HAL/AP_HAL.h>
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#include <AP_Math/AP_Math.h>
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#include "Util.h"
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#include "GPIO.h"
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#if HAL_USE_I2C == TRUE && defined(HAL_I2C_DEVICE_LIST)
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#include "Scheduler.h"
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#include "hwdef/common/stm32_util.h"
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#include <AP_InternalError/AP_InternalError.h>
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#include "ch.h"
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#include "hal.h"
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static const struct I2CInfo {
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I2CDriver *i2c;
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uint8_t instance;
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uint8_t dma_channel_rx;
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uint8_t dma_channel_tx;
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ioline_t scl_line;
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ioline_t sda_line;
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} I2CD[] = { HAL_I2C_DEVICE_LIST };
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using namespace ChibiOS;
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extern const AP_HAL::HAL& hal;
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I2CBus I2CDeviceManager::businfo[ARRAY_SIZE(I2CD)];
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#ifndef HAL_I2C_BUS_BASE
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#define HAL_I2C_BUS_BASE 0
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#endif
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// default to 100kHz clock for maximum reliability. This can be
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// changed in hwdef.dat
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#ifndef HAL_I2C_MAX_CLOCK
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#define HAL_I2C_MAX_CLOCK 100000
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#endif
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// values calculated with STM32CubeMX tool, PCLK=54MHz
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#ifndef HAL_I2C_F7_100_TIMINGR
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#define HAL_I2C_F7_100_TIMINGR 0x30812E3E
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#endif
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#ifndef HAL_I2C_F7_400_TIMINGR
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#define HAL_I2C_F7_400_TIMINGR 0x6000030D
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#endif
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#ifndef HAL_I2C_H7_100_TIMINGR
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#define HAL_I2C_H7_100_TIMINGR 0x00707CBB
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#endif
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#ifndef HAL_I2C_H7_400_TIMINGR
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#define HAL_I2C_H7_400_TIMINGR 0x00300F38
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#endif
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#ifndef HAL_I2C_L4_100_TIMINGR
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#define HAL_I2C_L4_100_TIMINGR 0x10909CEC
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#endif
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#ifndef HAL_I2C_L4_400_TIMINGR
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#define HAL_I2C_L4_400_TIMINGR 0x00702991
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#endif
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#ifndef HAL_I2C_G4_100_TIMINGR
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#define HAL_I2C_G4_100_TIMINGR 0x60505F8C
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#endif
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#ifndef HAL_I2C_G4_400_TIMINGR
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#define HAL_I2C_G4_400_TIMINGR 0x20501E65
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#endif
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/*
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enable clear (toggling SCL) on I2C bus timeouts which leave SDA stuck low
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*/
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#ifndef HAL_I2C_CLEAR_ON_TIMEOUT
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#define HAL_I2C_CLEAR_ON_TIMEOUT 1
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#endif
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// get a handle for DMA sharing DMA channels with other subsystems
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void I2CBus::dma_init(void)
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{
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chMtxObjectInit(&dma_lock);
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dma_handle = new Shared_DMA(I2CD[busnum].dma_channel_tx, I2CD[busnum].dma_channel_rx,
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FUNCTOR_BIND_MEMBER(&I2CBus::dma_allocate, void, Shared_DMA *),
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FUNCTOR_BIND_MEMBER(&I2CBus::dma_deallocate, void, Shared_DMA *));
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}
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// Clear Bus to avoid bus lockup
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void I2CBus::clear_all()
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{
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for (uint8_t i=0; i<ARRAY_SIZE(I2CD); i++) {
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clear_bus(i);
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}
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}
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/*
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If bus exists, set its data and clock lines to floating
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*/
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void I2CBus::set_bus_to_floating(uint8_t busidx)
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{
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if (busidx < ARRAY_SIZE(I2CD)) {
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const struct I2CInfo &info = I2CD[busidx];
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const ioline_t sda_line = GPIO::resolve_alt_config(info.sda_line, PERIPH_TYPE::I2C_SDA, info.instance);
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const ioline_t scl_line = GPIO::resolve_alt_config(info.scl_line, PERIPH_TYPE::I2C_SCL, info.instance);
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palSetLineMode(sda_line, PAL_MODE_INPUT);
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palSetLineMode(scl_line, PAL_MODE_INPUT);
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}
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}
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/*
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Check enabled I2C/CAN select pins against check_pins bitmask
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*/
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bool I2CBus::check_select_pins(uint8_t check_pins)
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{
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uint8_t enabled_pins = 0;
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#ifdef HAL_GPIO_PIN_GPIO_CAN_I2C1_SEL
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enabled_pins |= palReadLine(HAL_GPIO_PIN_GPIO_CAN_I2C1_SEL) << 0;
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#endif
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#ifdef HAL_GPIO_PIN_GPIO_CAN_I2C2_SEL
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enabled_pins |= palReadLine(HAL_GPIO_PIN_GPIO_CAN_I2C2_SEL) << 1;
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#endif
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#ifdef HAL_GPIO_PIN_GPIO_CAN_I2C3_SEL
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enabled_pins |= palReadLine(HAL_GPIO_PIN_GPIO_CAN_I2C3_SEL) << 2;
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#endif
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#ifdef HAL_GPIO_PIN_GPIO_CAN_I2C4_SEL
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enabled_pins |= palReadLine(HAL_GPIO_PIN_GPIO_CAN_I2C4_SEL) << 3;
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#endif
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return (enabled_pins & check_pins) == check_pins;
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}
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/*
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clear a stuck bus (bus held by a device that is holding SDA low) by
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clocking out pulses on SCL to let the device complete its
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transaction
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*/
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void I2CBus::clear_bus(uint8_t busidx)
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{
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#if HAL_I2C_CLEAR_ON_TIMEOUT
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const struct I2CInfo &info = I2CD[busidx];
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const ioline_t scl_line = GPIO::resolve_alt_config(info.scl_line, PERIPH_TYPE::I2C_SCL, info.instance);
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if (scl_line == 0) {
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return;
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}
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const iomode_t mode_saved = palReadLineMode(scl_line);
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palSetLineMode(scl_line, PAL_MODE_OUTPUT_PUSHPULL);
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for(uint8_t j = 0; j < 20; j++) {
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palToggleLine(scl_line);
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hal.scheduler->delay_microseconds(10);
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}
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palSetLineMode(scl_line, mode_saved);
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#endif
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}
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#if HAL_I2C_CLEAR_ON_TIMEOUT
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/*
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read SDA on a bus, to check if it may be stuck
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*/
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uint8_t I2CBus::read_sda(uint8_t busidx)
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{
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const struct I2CInfo &info = I2CD[busidx];
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const ioline_t sda_line = GPIO::resolve_alt_config(info.sda_line, PERIPH_TYPE::I2C_SDA, info.instance);
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if (sda_line == 0) {
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return 0;
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}
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const iomode_t mode_saved = palReadLineMode(sda_line);
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palSetLineMode(sda_line, PAL_MODE_INPUT);
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uint8_t ret = palReadLine(sda_line);
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palSetLineMode(sda_line, mode_saved);
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return ret;
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}
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#endif
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// setup I2C buses
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I2CDeviceManager::I2CDeviceManager(void)
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{
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for (uint8_t i=0; i<ARRAY_SIZE(I2CD); i++) {
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businfo[i].busnum = i;
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businfo[i].dma_init();
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/*
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setup default I2C config. As each device is opened we will
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drop the speed to be the minimum speed requested
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*/
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businfo[i].busclock = HAL_I2C_MAX_CLOCK;
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#if defined(STM32F7) || defined(STM32F3)
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if (businfo[i].busclock <= 100000) {
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businfo[i].i2ccfg.timingr = HAL_I2C_F7_100_TIMINGR;
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businfo[i].busclock = 100000;
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} else {
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businfo[i].i2ccfg.timingr = HAL_I2C_F7_400_TIMINGR;
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businfo[i].busclock = 400000;
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}
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#elif defined(STM32H7)
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if (businfo[i].busclock <= 100000) {
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businfo[i].i2ccfg.timingr = HAL_I2C_H7_100_TIMINGR;
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businfo[i].busclock = 100000;
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} else {
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businfo[i].i2ccfg.timingr = HAL_I2C_H7_400_TIMINGR;
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businfo[i].busclock = 400000;
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}
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#elif defined(STM32L4)
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if (businfo[i].busclock <= 100000) {
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businfo[i].i2ccfg.timingr = HAL_I2C_L4_100_TIMINGR;
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businfo[i].busclock = 100000;
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} else {
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businfo[i].i2ccfg.timingr = HAL_I2C_L4_400_TIMINGR;
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businfo[i].busclock = 400000;
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}
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#elif defined(STM32G4)
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if (businfo[i].busclock <= 100000) {
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businfo[i].i2ccfg.timingr = HAL_I2C_G4_100_TIMINGR;
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businfo[i].busclock = 100000;
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} else {
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businfo[i].i2ccfg.timingr = HAL_I2C_G4_400_TIMINGR;
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businfo[i].busclock = 400000;
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}
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#else // F1 or F4
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businfo[i].i2ccfg.op_mode = OPMODE_I2C;
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businfo[i].i2ccfg.clock_speed = businfo[i].busclock;
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if (businfo[i].i2ccfg.clock_speed <= 100000) {
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businfo[i].i2ccfg.duty_cycle = STD_DUTY_CYCLE;
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} else {
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businfo[i].i2ccfg.duty_cycle = FAST_DUTY_CYCLE_2;
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}
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#endif
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}
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}
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I2CDevice::I2CDevice(uint8_t busnum, uint8_t address, uint32_t bus_clock, bool use_smbus, uint32_t timeout_ms) :
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_retries(2),
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_address(address),
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_use_smbus(use_smbus),
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_timeout_ms(timeout_ms),
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bus(I2CDeviceManager::businfo[busnum])
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{
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set_device_bus(busnum+HAL_I2C_BUS_BASE);
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set_device_address(address);
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asprintf(&pname, "I2C:%u:%02x",
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(unsigned)busnum, (unsigned)address);
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if (bus_clock < bus.busclock) {
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32F3) || defined(STM32G4) || defined(STM32L4)
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if (bus_clock <= 100000) {
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bus.i2ccfg.timingr = HAL_I2C_F7_100_TIMINGR;
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bus.busclock = 100000;
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}
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#else
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bus.i2ccfg.clock_speed = bus_clock;
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bus.busclock = bus_clock;
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if (bus_clock <= 100000) {
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bus.i2ccfg.duty_cycle = STD_DUTY_CYCLE;
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}
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#endif
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DEV_PRINTF("I2C%u clock %ukHz\n", busnum, unsigned(bus.busclock/1000));
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}
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}
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I2CDevice::~I2CDevice()
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{
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#if 0
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printf("I2C device bus %u address 0x%02x closed\n",
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(unsigned)bus.busnum, (unsigned)_address);
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#endif
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free(pname);
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}
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/*
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allocate DMA channel, nothing to do, as we don't keep the bus active between transactions
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*/
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void I2CBus::dma_allocate(Shared_DMA *ctx)
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{
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}
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/*
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deallocate DMA channel
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*/
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void I2CBus::dma_deallocate(Shared_DMA *)
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{
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}
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bool I2CDevice::transfer(const uint8_t *send, uint32_t send_len,
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uint8_t *recv, uint32_t recv_len)
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{
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if (!bus.semaphore.check_owner()) {
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DEV_PRINTF("I2C: not owner of 0x%x for addr 0x%02x\n", (unsigned)get_bus_id(), _address);
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return false;
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}
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32F3) || defined(STM32G4) || defined(STM32L4)
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if (_use_smbus) {
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bus.i2ccfg.cr1 |= I2C_CR1_SMBHEN;
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} else {
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bus.i2ccfg.cr1 &= ~I2C_CR1_SMBHEN;
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}
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#else
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if (_use_smbus) {
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bus.i2ccfg.op_mode = OPMODE_SMBUS_HOST;
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} else {
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bus.i2ccfg.op_mode = OPMODE_I2C;
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}
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#endif
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if (_split_transfers) {
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/*
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splitting the transfer() into two pieces avoids a stop condition
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with SCL low which is not supported on some devices (such as
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LidarLite blue label)
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*/
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if (send && send_len) {
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if (!_transfer(send, send_len, nullptr, 0)) {
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return false;
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}
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}
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if (recv && recv_len) {
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if (!_transfer(nullptr, 0, recv, recv_len)) {
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return false;
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}
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}
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} else {
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// combined transfer
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if (!_transfer(send, send_len, recv, recv_len)) {
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return false;
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}
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}
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return true;
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}
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bool I2CDevice::_transfer(const uint8_t *send, uint32_t send_len,
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uint8_t *recv, uint32_t recv_len)
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{
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i2cAcquireBus(I2CD[bus.busnum].i2c);
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if (!bus.bouncebuffer_setup(send, send_len, recv, recv_len)) {
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i2cReleaseBus(I2CD[bus.busnum].i2c);
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return false;
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}
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for(uint8_t i=0 ; i <= _retries; i++) {
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int ret;
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// calculate a timeout as twice the expected transfer time, and set as min of 4ms
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uint32_t timeout_ms = 1+2*(((8*1000000UL/bus.busclock)*(send_len+recv_len))/1000);
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timeout_ms = MAX(timeout_ms, _timeout_ms);
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// we get the lock and start the bus inside the retry loop to
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// allow us to give up the DMA channel to an SPI device on
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// retries
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bus.dma_handle->lock();
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i2cStart(I2CD[bus.busnum].i2c, &bus.i2ccfg);
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osalDbgAssert(I2CD[bus.busnum].i2c->state == I2C_READY, "i2cStart state");
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osalSysLock();
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hal.util->persistent_data.i2c_count++;
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osalSysUnlock();
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if(send_len == 0) {
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ret = i2cMasterReceiveTimeout(I2CD[bus.busnum].i2c, _address, recv, recv_len, chTimeMS2I(timeout_ms));
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} else {
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ret = i2cMasterTransmitTimeout(I2CD[bus.busnum].i2c, _address, send, send_len,
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recv, recv_len, chTimeMS2I(timeout_ms));
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}
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i2cSoftStop(I2CD[bus.busnum].i2c);
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osalDbgAssert(I2CD[bus.busnum].i2c->state == I2C_STOP, "i2cStart state");
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bus.dma_handle->unlock();
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if (I2CD[bus.busnum].i2c->errors & I2C_ISR_LIMIT) {
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INTERNAL_ERROR(AP_InternalError::error_t::i2c_isr);
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break;
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}
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#ifdef STM32_I2C_ISR_LIMIT
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AP_HAL::Util::PersistentData &pd = hal.util->persistent_data;
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pd.i2c_isr_count += I2CD[bus.busnum].i2c->isr_count;
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#endif
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if (ret == MSG_OK) {
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bus.bouncebuffer_finish(send, recv, recv_len);
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i2cReleaseBus(I2CD[bus.busnum].i2c);
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return true;
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}
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#if HAL_I2C_CLEAR_ON_TIMEOUT
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if (ret == MSG_TIMEOUT && I2CBus::read_sda(bus.busnum) == 0) {
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I2CBus::clear_bus(bus.busnum);
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}
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#endif
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}
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bus.bouncebuffer_finish(send, recv, recv_len);
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i2cReleaseBus(I2CD[bus.busnum].i2c);
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return false;
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}
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bool I2CDevice::read_registers_multiple(uint8_t first_reg, uint8_t *recv,
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uint32_t recv_len, uint8_t times)
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{
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return false;
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}
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/*
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register a periodic callback
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*/
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AP_HAL::Device::PeriodicHandle I2CDevice::register_periodic_callback(uint32_t period_usec, AP_HAL::Device::PeriodicCb cb)
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{
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return bus.register_periodic_callback(period_usec, cb, this);
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}
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/*
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adjust a periodic callback
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*/
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bool I2CDevice::adjust_periodic_callback(AP_HAL::Device::PeriodicHandle h, uint32_t period_usec)
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{
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return bus.adjust_timer(h, period_usec);
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}
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AP_HAL::OwnPtr<AP_HAL::I2CDevice>
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I2CDeviceManager::get_device(uint8_t bus, uint8_t address,
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uint32_t bus_clock,
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bool use_smbus,
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uint32_t timeout_ms)
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{
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bus -= HAL_I2C_BUS_BASE;
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if (bus >= ARRAY_SIZE(I2CD)) {
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return AP_HAL::OwnPtr<AP_HAL::I2CDevice>(nullptr);
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}
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auto dev = AP_HAL::OwnPtr<AP_HAL::I2CDevice>(new I2CDevice(bus, address, bus_clock, use_smbus, timeout_ms));
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return dev;
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}
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/*
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get mask of bus numbers for all configured I2C buses
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*/
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uint32_t I2CDeviceManager::get_bus_mask(void) const
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{
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return ((1U << ARRAY_SIZE(I2CD)) - 1) << HAL_I2C_BUS_BASE;
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}
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/*
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get mask of bus numbers for all configured internal I2C buses
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*/
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uint32_t I2CDeviceManager::get_bus_mask_internal(void) const
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{
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// assume first bus is internal
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return get_bus_mask() & HAL_I2C_INTERNAL_MASK;
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}
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/*
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get mask of bus numbers for all configured external I2C buses
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*/
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uint32_t I2CDeviceManager::get_bus_mask_external(void) const
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{
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// assume first bus is internal
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return get_bus_mask() & ~HAL_I2C_INTERNAL_MASK;
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}
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#endif // HAL_USE_I2C
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