mirror of
https://github.com/ArduPilot/ardupilot
synced 2025-01-03 14:38:30 -04:00
5287fb2e1b
This implements a max quota of GPIO interrupts per 100ms period to prevent high interrupt counts from consuming all CPU and causing a lockup. The limit is set as 10k interrupts per 0.1s period. That limit should be high enough for all reasonable uses of GPIO interrupt handlers while being below the level that causes significant CPU loads and flight issues This addresses issue #15384
414 lines
11 KiB
C++
414 lines
11 KiB
C++
/*
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* This file is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Code by Andrew Tridgell and Siddharth Bharat Purohit
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*/
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#include "GPIO.h"
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#include <AP_BoardConfig/AP_BoardConfig.h>
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#include "hwdef/common/stm32_util.h"
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#include <AP_InternalError/AP_InternalError.h>
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#ifndef HAL_NO_UARTDRIVER
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#include <GCS_MAVLink/GCS.h>
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#endif
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using namespace ChibiOS;
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// GPIO pin table from hwdef.dat
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static struct gpio_entry {
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uint8_t pin_num;
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bool enabled;
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uint8_t pwm_num;
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ioline_t pal_line;
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AP_HAL::GPIO::irq_handler_fn_t fn; // callback for GPIO interface
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bool is_input;
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uint8_t mode;
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thread_reference_t thd_wait;
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uint16_t isr_quota;
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} _gpio_tab[] = HAL_GPIO_PINS;
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#define NUM_PINS ARRAY_SIZE(_gpio_tab)
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#define PIN_ENABLED(pin) ((pin)<NUM_PINS && _gpio_tab[pin].enabled)
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/*
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map a user pin number to a GPIO table entry
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*/
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static struct gpio_entry *gpio_by_pin_num(uint8_t pin_num, bool check_enabled=true)
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{
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for (uint8_t i=0; i<ARRAY_SIZE(_gpio_tab); i++) {
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if (pin_num == _gpio_tab[i].pin_num) {
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if (check_enabled && !_gpio_tab[i].enabled) {
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return NULL;
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}
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return &_gpio_tab[i];
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}
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}
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return NULL;
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}
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static void pal_interrupt_cb(void *arg);
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static void pal_interrupt_cb_functor(void *arg);
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GPIO::GPIO()
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{}
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void GPIO::init()
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{
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// auto-disable pins being used for PWM output based on BRD_PWM_COUNT parameter
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uint8_t pwm_count = AP_BoardConfig::get_pwm_count();
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for (uint8_t i=0; i<ARRAY_SIZE(_gpio_tab); i++) {
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struct gpio_entry *g = &_gpio_tab[i];
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if (g->pwm_num != 0) {
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g->enabled = g->pwm_num > pwm_count;
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}
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}
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#ifdef HAL_PIN_ALT_CONFIG
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setup_alt_config();
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#endif
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}
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#ifdef HAL_PIN_ALT_CONFIG
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/*
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alternative config table, selected using BRD_ALT_CONFIG
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*/
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static const struct alt_config {
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uint8_t alternate;
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uint16_t mode;
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ioline_t line;
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} alternate_config[] HAL_PIN_ALT_CONFIG;
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/*
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change pin configuration based on ALT() lines in hwdef.dat
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*/
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void GPIO::setup_alt_config(void)
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{
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AP_BoardConfig *bc = AP::boardConfig();
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if (!bc) {
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return;
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}
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const uint8_t alt = bc->get_alt_config();
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if (alt == 0) {
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// use defaults
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return;
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}
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for (uint8_t i=0; i<ARRAY_SIZE(alternate_config); i++) {
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if (alt == alternate_config[i].alternate) {
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const iomode_t mode = alternate_config[i].mode & ~PAL_STM32_HIGH;
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const uint8_t odr = (alternate_config[i].mode & PAL_STM32_HIGH)?1:0;
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palSetLineMode(alternate_config[i].line, mode);
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palWriteLine(alternate_config[i].line, odr);
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}
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}
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}
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#endif // HAL_PIN_ALT_CONFIG
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void GPIO::pinMode(uint8_t pin, uint8_t output)
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{
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struct gpio_entry *g = gpio_by_pin_num(pin);
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if (g) {
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if (!output && g->is_input &&
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(g->mode == PAL_MODE_INPUT_PULLUP ||
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g->mode == PAL_MODE_INPUT_PULLDOWN)) {
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// already set
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return;
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}
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g->mode = output?PAL_MODE_OUTPUT_PUSHPULL:PAL_MODE_INPUT;
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32F4)
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if (g->mode == PAL_MODE_OUTPUT_PUSHPULL) {
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// retain OPENDRAIN if already set
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iomode_t old_mode = palReadLineMode(g->pal_line);
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if ((old_mode & PAL_MODE_OUTPUT_OPENDRAIN) == PAL_MODE_OUTPUT_OPENDRAIN) {
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g->mode = PAL_MODE_OUTPUT_OPENDRAIN;
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}
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}
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#endif
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palSetLineMode(g->pal_line, g->mode);
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g->is_input = !output;
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}
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}
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uint8_t GPIO::read(uint8_t pin)
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{
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struct gpio_entry *g = gpio_by_pin_num(pin);
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if (g) {
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return palReadLine(g->pal_line);
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}
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return 0;
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}
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void GPIO::write(uint8_t pin, uint8_t value)
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{
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struct gpio_entry *g = gpio_by_pin_num(pin);
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if (g) {
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if (g->is_input) {
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// control pullup/pulldown
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g->mode = value==1?PAL_MODE_INPUT_PULLUP:PAL_MODE_INPUT_PULLDOWN;
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palSetLineMode(g->pal_line, g->mode);
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} else if (value == PAL_LOW) {
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palClearLine(g->pal_line);
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} else {
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palSetLine(g->pal_line);
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}
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}
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}
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void GPIO::toggle(uint8_t pin)
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{
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struct gpio_entry *g = gpio_by_pin_num(pin);
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if (g) {
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palToggleLine(g->pal_line);
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}
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}
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/* Alternative interface: */
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AP_HAL::DigitalSource* GPIO::channel(uint16_t pin)
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{
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struct gpio_entry *g = gpio_by_pin_num(pin);
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if (!g) {
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return nullptr;
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}
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return new DigitalSource(g->pal_line);
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}
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extern const AP_HAL::HAL& hal;
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/*
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Attach an interrupt handler to a GPIO pin number. The pin number
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must be one specified with a GPIO() marker in hwdef.dat
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*/
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bool GPIO::attach_interrupt(uint8_t pin,
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irq_handler_fn_t fn,
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INTERRUPT_TRIGGER_TYPE mode)
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{
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struct gpio_entry *g = gpio_by_pin_num(pin, false);
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if (!g) {
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return false;
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}
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if (!_attach_interrupt(g->pal_line,
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palcallback_t(fn?pal_interrupt_cb_functor:nullptr),
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g,
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mode)) {
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return false;
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}
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g->fn = fn;
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return true;
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}
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/*
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Attach an interrupt handler to ioline_t
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*/
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bool GPIO::_attach_interrupt(ioline_t line, AP_HAL::Proc p, uint8_t mode)
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{
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return _attach_interrupt(line, palcallback_t(p?pal_interrupt_cb:nullptr), (void*)p, mode);
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}
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bool GPIO::attach_interrupt(uint8_t pin,
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AP_HAL::Proc proc,
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INTERRUPT_TRIGGER_TYPE mode) {
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struct gpio_entry *g = gpio_by_pin_num(pin, false);
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if (!g) {
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return false;
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}
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return _attach_interrupt(g->pal_line, proc, mode);
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}
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bool GPIO::_attach_interruptI(ioline_t line, palcallback_t cb, void *p, uint8_t mode)
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{
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uint32_t chmode = 0;
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switch(mode) {
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case INTERRUPT_FALLING:
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chmode = PAL_EVENT_MODE_FALLING_EDGE;
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break;
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case INTERRUPT_RISING:
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chmode = PAL_EVENT_MODE_RISING_EDGE;
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break;
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case INTERRUPT_BOTH:
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chmode = PAL_EVENT_MODE_BOTH_EDGES;
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break;
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default:
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if (p) {
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return false;
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}
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break;
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}
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palevent_t *pep = pal_lld_get_line_event(line);
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if (pep->cb && p != nullptr) {
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// the pad is already being used for a callback
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return false;
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}
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if (!p) {
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chmode = PAL_EVENT_MODE_DISABLED;
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}
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palDisableLineEventI(line);
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palSetLineCallbackI(line, cb, p);
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palEnableLineEventI(line, chmode);
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return true;
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}
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bool GPIO::_attach_interrupt(ioline_t line, palcallback_t cb, void *p, uint8_t mode)
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{
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osalSysLock();
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bool ret = _attach_interruptI(line, cb, p, mode);
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osalSysUnlock();
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return ret;
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}
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bool GPIO::usb_connected(void)
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{
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return _usb_connected;
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}
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DigitalSource::DigitalSource(ioline_t _line) :
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line(_line)
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{}
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void DigitalSource::mode(uint8_t output)
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{
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palSetLineMode(line, output);
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}
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uint8_t DigitalSource::read()
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{
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return palReadLine(line);
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}
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void DigitalSource::write(uint8_t value)
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{
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palWriteLine(line, value);
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}
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void DigitalSource::toggle()
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{
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palToggleLine(line);
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}
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static void pal_interrupt_cb(void *arg)
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{
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if (arg != nullptr) {
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((AP_HAL::Proc)arg)();
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}
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}
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static void pal_interrupt_cb_functor(void *arg)
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{
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const uint32_t now = AP_HAL::micros();
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struct gpio_entry *g = (gpio_entry *)arg;
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if (g == nullptr) {
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// what?
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return;
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}
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if (!(g->fn)) {
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return;
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}
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if (g->isr_quota >= 1) {
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/*
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we have an interrupt quota enabled for this pin. If the
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quota remaining drops to 1 without it being refreshed in
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timer_tick then we disable the interrupt source. This is to
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prevent CPU overload due to very high GPIO interrupt counts
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*/
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if (g->isr_quota == 1) {
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osalSysLockFromISR();
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palDisableLineEventI(g->pal_line);
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osalSysUnlockFromISR();
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return;
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}
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g->isr_quota--;
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}
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(g->fn)(g->pin_num, palReadLine(g->pal_line), now);
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}
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/*
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handle interrupt from pin change for wait_pin()
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*/
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static void pal_interrupt_wait(void *arg)
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{
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osalSysLockFromISR();
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struct gpio_entry *g = (gpio_entry *)arg;
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if (g == nullptr || g->thd_wait == nullptr) {
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osalSysUnlockFromISR();
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return;
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}
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osalThreadResumeI(&g->thd_wait, MSG_OK);
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osalSysUnlockFromISR();
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}
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/*
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block waiting for a pin to change. A timeout of 0 means wait
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forever. Return true on pin change, false on timeout
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*/
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bool GPIO::wait_pin(uint8_t pin, INTERRUPT_TRIGGER_TYPE mode, uint32_t timeout_us)
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{
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struct gpio_entry *g = gpio_by_pin_num(pin);
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if (!g) {
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return false;
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}
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osalSysLock();
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if (g->thd_wait) {
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// only allow single waiter
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osalSysUnlock();
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return false;
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}
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if (!_attach_interruptI(g->pal_line,
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palcallback_t(pal_interrupt_wait),
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g,
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mode)) {
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osalSysUnlock();
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return false;
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}
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msg_t msg = osalThreadSuspendTimeoutS(&g->thd_wait, TIME_US2I(timeout_us));
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_attach_interruptI(g->pal_line,
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palcallback_t(nullptr),
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nullptr,
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mode);
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osalSysUnlock();
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return msg == MSG_OK;
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}
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#ifndef IOMCU_FW
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/*
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timer to setup interrupt quotas for a 100ms period from
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monitor thread
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*/
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void GPIO::timer_tick()
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{
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// allow 100k interrupts/second max for GPIO interrupt sources, which is
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// 10k per 100ms call to timer_tick()
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const uint16_t quota = 10000U;
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for (uint8_t i=0; i<ARRAY_SIZE(_gpio_tab); i++) {
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if (_gpio_tab[i].isr_quota == 1) {
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// we ran out of ISR quota for this pin since the last
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// check. This is not really an internal error, but we use
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// INTERNAL_ERROR() to get the reporting mechanism
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#ifndef HAL_NO_UARTDRIVER
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GCS_SEND_TEXT(MAV_SEVERITY_ERROR,"ISR flood on pin %u", _gpio_tab[i].pin_num);
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#endif
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INTERNAL_ERROR(AP_InternalError::error_t::gpio_isr);
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}
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_gpio_tab[i].isr_quota = quota;
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}
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}
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#endif // IOMCU_FW
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