mirror of
https://github.com/ArduPilot/ardupilot
synced 2025-01-04 15:08:28 -04:00
85c0c98194
In _start_conversion(), the check for return code of _dev->transfer() was inverted. The structure also needs to be PACKED, otherwise there will be a hole in the middle. Fix these issues and use be16_t where it makes sense. In read() we need to check for the second byte of config register, so either make it an array of uint8_t or convert from big endian to host endianness. It's simpler to leave it as it was, accessing just the first byte. Also the conversion value is in be16 type an needs to be converted to host endiannes, not the opposite. Fix bus number: all boards that use it expect it to be on bus 1, not 0.
240 lines
7.6 KiB
C++
240 lines
7.6 KiB
C++
#include <AP_HAL/AP_HAL.h>
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#include <AP_HAL/utility/sparse-endian.h>
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#include "AP_ADC_ADS1115.h"
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#define ADS1115_ADDRESS_ADDR_GND 0x48 // address pin low (GND)
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#define ADS1115_ADDRESS_ADDR_VDD 0x49 // address pin high (VCC)
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#define ADS1115_ADDRESS_ADDR_SDA 0x4A // address pin tied to SDA pin
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#define ADS1115_ADDRESS_ADDR_SCL 0x4B // address pin tied to SCL pin
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#define ADS1115_I2C_ADDR ADS1115_ADDRESS_ADDR_GND
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#define ADS1115_I2C_BUS 1
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#define ADS1115_RA_CONVERSION 0x00
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#define ADS1115_RA_CONFIG 0x01
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#define ADS1115_RA_LO_THRESH 0x02
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#define ADS1115_RA_HI_THRESH 0x03
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#define ADS1115_OS_SHIFT 15
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#define ADS1115_OS_INACTIVE 0x00 << ADS1115_OS_SHIFT
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#define ADS1115_OS_ACTIVE 0x01 << ADS1115_OS_SHIFT
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#define ADS1115_MUX_SHIFT 12
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#define ADS1115_MUX_P0_N1 0x00 << ADS1115_MUX_SHIFT /* default */
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#define ADS1115_MUX_P0_N3 0x01 << ADS1115_MUX_SHIFT
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#define ADS1115_MUX_P1_N3 0x02 << ADS1115_MUX_SHIFT
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#define ADS1115_MUX_P2_N3 0x03 << ADS1115_MUX_SHIFT
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#define ADS1115_MUX_P0_NG 0x04 << ADS1115_MUX_SHIFT
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#define ADS1115_MUX_P1_NG 0x05 << ADS1115_MUX_SHIFT
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#define ADS1115_MUX_P2_NG 0x06 << ADS1115_MUX_SHIFT
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#define ADS1115_MUX_P3_NG 0x07 << ADS1115_MUX_SHIFT
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#define ADS1115_PGA_SHIFT 9
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#define ADS1115_PGA_6P144 0x00 << ADS1115_PGA_SHIFT
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#define ADS1115_PGA_4P096 0x01 << ADS1115_PGA_SHIFT
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#define ADS1115_PGA_2P048 0x02 << ADS1115_PGA_SHIFT // default
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#define ADS1115_PGA_1P024 0x03 << ADS1115_PGA_SHIFT
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#define ADS1115_PGA_0P512 0x04 << ADS1115_PGA_SHIFT
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#define ADS1115_PGA_0P256 0x05 << ADS1115_PGA_SHIFT
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#define ADS1115_PGA_0P256B 0x06 << ADS1115_PGA_SHIFT
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#define ADS1115_PGA_0P256C 0x07 << ADS1115_PGA_SHIFT
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#define ADS1115_MV_6P144 0.187500f
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#define ADS1115_MV_4P096 0.125000f
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#define ADS1115_MV_2P048 0.062500f // default
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#define ADS1115_MV_1P024 0.031250f
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#define ADS1115_MV_0P512 0.015625f
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#define ADS1115_MV_0P256 0.007813f
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#define ADS1115_MV_0P256B 0.007813f
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#define ADS1115_MV_0P256C 0.007813f
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#define ADS1115_MODE_SHIFT 8
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#define ADS1115_MODE_CONTINUOUS 0x00 << ADS1115_MODE_SHIFT
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#define ADS1115_MODE_SINGLESHOT 0x01 << ADS1115_MODE_SHIFT // default
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#define ADS1115_RATE_SHIFT 5
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#define ADS1115_RATE_8 0x00 << ADS1115_RATE_SHIFT
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#define ADS1115_RATE_16 0x01 << ADS1115_RATE_SHIFT
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#define ADS1115_RATE_32 0x02 << ADS1115_RATE_SHIFT
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#define ADS1115_RATE_64 0x03 << ADS1115_RATE_SHIFT
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#define ADS1115_RATE_128 0x04 << ADS1115_RATE_SHIFT // default
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#define ADS1115_RATE_250 0x05 << ADS1115_RATE_SHIFT
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#define ADS1115_RATE_475 0x06 << ADS1115_RATE_SHIFT
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#define ADS1115_RATE_860 0x07 << ADS1115_RATE_SHIFT
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#define ADS1115_COMP_MODE_SHIFT 4
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#define ADS1115_COMP_MODE_HYSTERESIS 0x00 << ADS1115_COMP_MODE_SHIFT // default
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#define ADS1115_COMP_MODE_WINDOW 0x01 << ADS1115_COMP_MODE_SHIFT
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#define ADS1115_COMP_POL_SHIFT 3
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#define ADS1115_COMP_POL_ACTIVE_LOW 0x00 << ADS1115_COMP_POL_SHIFT // default
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#define ADS1115_COMP_POL_ACTIVE_HIGH 0x01 << ADS1115_COMP_POL_SHIFT
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#define ADS1115_COMP_LAT_SHIFT 2
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#define ADS1115_COMP_LAT_NON_LATCHING 0x00 << ADS1115_COMP_LAT_SHIFT // default
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#define ADS1115_COMP_LAT_LATCHING 0x01 << ADS1115_COMP_LAT_SHIFT
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#define ADS1115_COMP_QUE_SHIFT 0
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#define ADS1115_COMP_QUE_ASSERT1 0x00 << ADS1115_COMP_SHIFT
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#define ADS1115_COMP_QUE_ASSERT2 0x01 << ADS1115_COMP_SHIFT
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#define ADS1115_COMP_QUE_ASSERT4 0x02 << ADS1115_COMP_SHIFT
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#define ADS1115_COMP_QUE_DISABLE 0x03 // default
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#define ADS1115_DEBUG 0
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#if ADS1115_DEBUG
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#include <cstdio>
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#define debug(fmt, args ...) do {hal.console->printf("%s:%d: " fmt "\n", __FUNCTION__, __LINE__, ## args); } while(0)
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#define error(fmt, args ...) do {fprintf(stderr,"%s:%d: " fmt "\n", __FUNCTION__, __LINE__, ## args); } while(0)
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#else
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#define debug(fmt, args ...)
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#define error(fmt, args ...)
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#endif
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extern const AP_HAL::HAL &hal;
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#define ADS1115_CHANNELS_COUNT 6
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const uint8_t AP_ADC_ADS1115::_channels_number = ADS1115_CHANNELS_COUNT;
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/* Only two differential channels used */
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static const uint16_t mux_table[ADS1115_CHANNELS_COUNT] = {
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ADS1115_MUX_P1_N3,
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ADS1115_MUX_P2_N3,
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ADS1115_MUX_P0_NG,
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ADS1115_MUX_P1_NG,
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ADS1115_MUX_P2_NG,
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ADS1115_MUX_P3_NG
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};
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AP_ADC_ADS1115::AP_ADC_ADS1115()
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: _dev(hal.i2c_mgr->get_device(ADS1115_I2C_BUS, ADS1115_I2C_ADDR))
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, _channel_to_read(0)
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{
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_samples = new adc_report_s[_channels_number];
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}
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bool AP_ADC_ADS1115::init()
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{
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hal.scheduler->suspend_timer_procs();
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_gain = ADS1115_PGA_4P096;
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hal.scheduler->register_timer_process(FUNCTOR_BIND_MEMBER(&AP_ADC_ADS1115::_update, void));
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hal.scheduler->resume_timer_procs();
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return true;
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}
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bool AP_ADC_ADS1115::_start_conversion(uint8_t channel)
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{
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struct PACKED {
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uint8_t reg;
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be16_t val;
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} config;
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config.reg = ADS1115_RA_CONFIG;
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config.val = htobe16(ADS1115_OS_ACTIVE | _gain | mux_table[channel] |
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ADS1115_MODE_SINGLESHOT | ADS1115_COMP_QUE_DISABLE |
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ADS1115_RATE_250);
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return _dev->transfer((uint8_t *)&config, sizeof(config), nullptr, 0);
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}
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size_t AP_ADC_ADS1115::read(adc_report_s *report, size_t length) const
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{
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for (size_t i = 0; i < length; i++) {
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report[i].data = _samples[i].data;
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report[i].id = _samples[i].id;
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}
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return length;
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}
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float AP_ADC_ADS1115::_convert_register_data_to_mv(int16_t word) const
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{
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float pga;
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switch (_gain) {
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case ADS1115_PGA_6P144:
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pga = ADS1115_MV_6P144;
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break;
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case ADS1115_PGA_4P096:
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pga = ADS1115_MV_4P096;
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break;
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case ADS1115_PGA_2P048:
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pga = ADS1115_MV_2P048;
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break;
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case ADS1115_PGA_1P024:
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pga = ADS1115_MV_1P024;
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break;
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case ADS1115_PGA_0P512:
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pga = ADS1115_MV_0P512;
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break;
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case ADS1115_PGA_0P256:
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pga = ADS1115_MV_0P256;
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break;
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case ADS1115_PGA_0P256B:
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pga = ADS1115_MV_0P256B;
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break;
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case ADS1115_PGA_0P256C:
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pga = ADS1115_MV_0P256C;
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break;
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default:
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pga = 0.0f;
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hal.console->printf("Wrong gain");
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AP_HAL::panic("ADS1115: wrong gain selected");
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break;
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}
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return (float) word * pga;
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}
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void AP_ADC_ADS1115::_update()
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{
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/* TODO: make update rate configurable */
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if (AP_HAL::micros() - _last_update_timestamp < 100000) {
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return;
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}
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uint8_t config[2];
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be16_t val;
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if (!_dev->get_semaphore()->take_nonblocking()) {
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return;
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}
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if (!_dev->read_registers(ADS1115_RA_CONFIG, config, sizeof(config))) {
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error("i2c->read_registers failed in ADS1115");
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_dev->get_semaphore()->give();
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return;
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}
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/* check rdy bit */
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if ((config[1] & 0x80) != 0x80 ) {
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_dev->get_semaphore()->give();
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return;
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}
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if (!_dev->read_registers(ADS1115_RA_CONVERSION, (uint8_t *)&val, sizeof(val))) {
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_dev->get_semaphore()->give();
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return;
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}
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float sample = _convert_register_data_to_mv(be16toh(val));
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_samples[_channel_to_read].data = sample;
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_samples[_channel_to_read].id = _channel_to_read;
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/* select next channel */
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_channel_to_read = (_channel_to_read + 1) % _channels_number;
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_start_conversion(_channel_to_read);
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_dev->get_semaphore()->give();
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_last_update_timestamp = AP_HAL::micros();
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}
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