mirror of
https://github.com/ArduPilot/ardupilot
synced 2025-01-04 15:08:28 -04:00
667b386356
convert RCOutput to new virtual timer interface cope with SDC vs SDMMC use new SPIv3 driver. Correct clocks for SDMMCv2. add STM32L431 support port ChibiOS config to version 8 support SPIv3 driver model v2 on H7 use currcore in debug options use new mmc API disable speed optimizations in the bootloader to save a little flash upgrade to halconf v8.4 relax constraints on QSP/flash clock. add support for disabling QSPI reset in main firmware
584 lines
16 KiB
C
584 lines
16 KiB
C
/*
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* This file is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "stm32_util.h"
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <stm32_dma.h>
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#include <hrt.h>
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static int64_t utc_time_offset;
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/*
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setup the timer capture digital filter for a channel
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*/
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void stm32_timer_set_input_filter(stm32_tim_t *tim, uint8_t channel, uint8_t filter_mode)
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{
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switch (channel) {
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case 0:
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tim->CCMR1 |= STM32_TIM_CCMR1_IC1F(filter_mode);
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break;
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case 1:
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tim->CCMR1 |= STM32_TIM_CCMR1_IC2F(filter_mode);
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break;
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case 2:
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tim->CCMR2 |= STM32_TIM_CCMR2_IC3F(filter_mode);
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break;
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case 3:
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tim->CCMR2 |= STM32_TIM_CCMR2_IC4F(filter_mode);
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break;
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}
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}
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/*
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set the input source of a timer channel
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*/
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void stm32_timer_set_channel_input(stm32_tim_t *tim, uint8_t channel, uint8_t input_source)
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{
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switch (channel) {
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case 0:
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tim->CCER &= ~STM32_TIM_CCER_CC1E;
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tim->CCMR1 &= ~STM32_TIM_CCMR1_CC1S_MASK;
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tim->CCMR1 |= STM32_TIM_CCMR1_CC1S(input_source);
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tim->CCER |= STM32_TIM_CCER_CC1E;
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break;
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case 1:
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tim->CCER &= ~STM32_TIM_CCER_CC2E;
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tim->CCMR1 &= ~STM32_TIM_CCMR1_CC2S_MASK;
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tim->CCMR1 |= STM32_TIM_CCMR1_CC2S(input_source);
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tim->CCER |= STM32_TIM_CCER_CC2E;
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break;
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case 2:
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tim->CCER &= ~STM32_TIM_CCER_CC3E;
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tim->CCMR2 &= ~STM32_TIM_CCMR2_CC3S_MASK;
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tim->CCMR2 |= STM32_TIM_CCMR2_CC3S(input_source);
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tim->CCER |= STM32_TIM_CCER_CC3E;
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break;
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case 3:
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tim->CCER &= ~STM32_TIM_CCER_CC4E;
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tim->CCMR2 &= ~STM32_TIM_CCMR2_CC4S_MASK;
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tim->CCMR2 |= STM32_TIM_CCMR2_CC4S(input_source);
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tim->CCER |= STM32_TIM_CCER_CC4E;
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break;
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}
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}
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#if CH_DBG_ENABLE_STACK_CHECK == TRUE && !defined(HAL_BOOTLOADER_BUILD)
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void show_stack_usage(void)
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{
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thread_t *tp;
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tp = chRegFirstThread();
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do {
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uint32_t stklimit = (uint32_t)tp->wabase;
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uint8_t *p = (uint8_t *)tp->wabase;
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while (*p == CH_DBG_STACK_FILL_VALUE) {
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p++;
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}
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uint32_t stack_left = ((uint32_t)p) - stklimit;
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printf("%s %u\n", tp->name, (unsigned)stack_left);
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tp = chRegNextThread(tp);
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} while (tp != NULL);
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}
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#endif
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/*
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set the utc time
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*/
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void stm32_set_utc_usec(uint64_t time_utc_usec)
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{
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uint64_t now = hrt_micros64();
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if (now <= time_utc_usec) {
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utc_time_offset = time_utc_usec - now;
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}
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}
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/*
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get system clock in UTC microseconds
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*/
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uint64_t stm32_get_utc_usec()
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{
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return hrt_micros64() + utc_time_offset;
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}
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struct utc_tm {
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uint8_t tm_year; // since 1900
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uint8_t tm_mon; // zero based
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uint8_t tm_mday; // zero based
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uint8_t tm_hour;
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uint8_t tm_min;
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uint8_t tm_sec;
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};
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/*
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return true if a year is a leap year
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*/
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static bool is_leap(uint32_t y)
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{
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y += 1900;
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return (y % 4) == 0 && ((y % 100) != 0 || (y % 400) == 0);
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}
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static const uint8_t ndays[2][12] ={
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{31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31},
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{31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}};
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/*
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parse a seconds since 1970 into a utc_tm structure
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code based on _der_gmtime from samba
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*/
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static void parse_utc_seconds(uint64_t utc_sec, struct utc_tm *tm)
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{
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uint32_t secday = utc_sec % (3600U * 24U);
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uint32_t days = utc_sec / (3600U * 24U);
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memset(tm, 0, sizeof(*tm));
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tm->tm_sec = secday % 60U;
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tm->tm_min = (secday % 3600U) / 60U;
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tm->tm_hour = secday / 3600U;
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tm->tm_year = 70;
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if (days > (2000 * 365)) {
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// don't look for dates too far into the future
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return;
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}
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while (true) {
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unsigned dayinyear = (is_leap(tm->tm_year) ? 366 : 365);
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if (days < dayinyear) {
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break;
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}
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tm->tm_year += 1;
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days -= dayinyear;
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}
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tm->tm_mon = 0;
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while (true) {
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unsigned daysinmonth = ndays[is_leap(tm->tm_year)?1:0][tm->tm_mon];
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if (days < daysinmonth) {
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break;
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}
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days -= daysinmonth;
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tm->tm_mon++;
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}
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tm->tm_mday = days + 1;
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}
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/*
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get time for fat filesystem. This is based on
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rtcConvertDateTimeToFAT from the ChibiOS RTC driver. We don't use
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the hw RTC clock as it is very inaccurate
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*/
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uint32_t get_fattime()
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{
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if (utc_time_offset == 0) {
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// return a fixed time
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return ((uint32_t)0 | (1 << 16)) | (1 << 21);
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}
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uint64_t utc_usec = stm32_get_utc_usec();
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uint64_t utc_sec = utc_usec / 1000000UL;
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struct utc_tm tm;
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parse_utc_seconds(utc_sec, &tm);
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uint32_t fattime;
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fattime = tm.tm_sec >> 1U;
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fattime |= tm.tm_min << 5U;
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fattime |= tm.tm_hour << 11U;
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fattime |= tm.tm_mday << 16U;
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fattime |= (tm.tm_mon+1) << 21U;
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fattime |= (uint32_t)((tm.tm_year-80) << 25U);
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return fattime;
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}
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#if AP_FASTBOOT_ENABLED
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// get RTC backup registers starting at given idx
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void get_rtc_backup(uint8_t idx, uint32_t *v, uint8_t n)
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{
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while (n--) {
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#if defined(STM32F1)
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(void)idx;
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__IO uint32_t *dr = (__IO uint32_t *)&BKP->DR1;
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*v++ = (dr[n/2]&0xFFFF) | (dr[n/2+1]<<16);
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#elif defined(STM32G4)
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*v++ = ((__IO uint32_t *)&TAMP->BKP0R)[idx++];
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#else
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*v++ = ((__IO uint32_t *)&RTC->BKP0R)[idx++];
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#endif
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}
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}
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// set n RTC backup registers starting at given idx
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void set_rtc_backup(uint8_t idx, const uint32_t *v, uint8_t n)
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{
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#if !defined(STM32F1)
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if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
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RCC->BDCR |= STM32_RTCSEL;
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RCC->BDCR |= RCC_BDCR_RTCEN;
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}
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#ifdef PWR_CR_DBP
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PWR->CR |= PWR_CR_DBP;
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#else
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PWR->CR1 |= PWR_CR1_DBP;
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#endif
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#endif
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while (n--) {
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#if defined(STM32F1)
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(void)idx;
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__IO uint32_t *dr = (__IO uint32_t *)&BKP->DR1;
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dr[n/2] = (*v) & 0xFFFF;
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dr[n/2+1] = (*v) >> 16;
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#elif defined(STM32G4)
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((__IO uint32_t *)&TAMP->BKP0R)[idx++] = *v++;
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#else
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((__IO uint32_t *)&RTC->BKP0R)[idx++] = *v++;
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#endif
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}
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}
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// see if RTC registers is setup for a fast reboot
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enum rtc_boot_magic check_fast_reboot(void)
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{
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uint32_t v;
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get_rtc_backup(0, &v, 1);
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return (enum rtc_boot_magic)v;
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}
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// set RTC register for a fast reboot
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void set_fast_reboot(enum rtc_boot_magic v)
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{
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if (check_fast_reboot() != v) {
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uint32_t vv = (uint32_t)v;
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set_rtc_backup(0, &vv, 1);
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}
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}
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#else // AP_FASTBOOT_ENABLED is not set
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// set n RTC backup registers starting at given idx
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void set_rtc_backup(uint8_t idx, const uint32_t *v, uint8_t n)
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{
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(void)idx;
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(void)v;
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(void)n;
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}
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// get RTC backup registers starting at given idx
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void get_rtc_backup(uint8_t idx, uint32_t *v, uint8_t n)
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{
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(void)idx;
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(void)v;
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(void)n;
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}
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#endif // AP_FASTBOOT_ENABLED
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/*
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enable peripheral power if needed This is done late to prevent
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problems with CTS causing SiK radios to stay in the bootloader. A
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SiK radio will stay in the bootloader if CTS is held to GND on boot
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*/
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void peripheral_power_enable(void)
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{
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#if defined(HAL_GPIO_PIN_nVDD_5V_PERIPH_EN) || defined(HAL_GPIO_PIN_VDD_5V_PERIPH_EN) || defined(HAL_GPIO_PIN_nVDD_5V_HIPOWER_EN) || defined(HAL_GPIO_PIN_VDD_3V3_SENSORS_EN)|| defined(HAL_GPIO_PIN_VDD_3V3_SENSORS2_EN) || defined(HAL_GPIO_PIN_VDD_3V3_SENSORS3_EN) || defined(HAL_GPIO_PIN_VDD_3V3_SENSORS4_EN) || defined(HAL_GPIO_PIN_nVDD_3V3_SD_CARD_EN) || defined(HAL_GPIO_PIN_VDD_3V3_SD_CARD_EN) || defined(HAL_GPIO_PIN_VDD_3V5_LTE_EN)
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// we don't know what state the bootloader had the CTS pin in, so
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// wait here with it pulled up from the PAL table for enough time
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// for the radio to be definately powered down
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uint8_t i;
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for (i=0; i<100; i++) {
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// use a loop as this may be a 16 bit timer
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chThdSleep(chTimeMS2I(1));
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}
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#ifdef HAL_GPIO_PIN_nVDD_5V_PERIPH_EN
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palWriteLine(HAL_GPIO_PIN_nVDD_5V_PERIPH_EN, 0);
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#endif
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#ifdef HAL_GPIO_PIN_VDD_5V_PERIPH_EN
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palWriteLine(HAL_GPIO_PIN_VDD_5V_PERIPH_EN, 1);
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#endif
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#ifdef HAL_GPIO_PIN_nVDD_5V_HIPOWER_EN
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palWriteLine(HAL_GPIO_PIN_nVDD_5V_HIPOWER_EN, 0);
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#endif
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#ifdef HAL_GPIO_PIN_VDD_5V_HIPOWER_EN
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palWriteLine(HAL_GPIO_PIN_VDD_5V_HIPOWER_EN, 1);
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#endif
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#ifdef HAL_GPIO_PIN_VDD_3V3_SENSORS_EN
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// the TBS-Colibri-F7 needs PE3 low at power on
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palWriteLine(HAL_GPIO_PIN_VDD_3V3_SENSORS_EN, 1);
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#endif
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#ifdef HAL_GPIO_PIN_VDD_3V3_SENSORS2_EN
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palWriteLine(HAL_GPIO_PIN_VDD_3V3_SENSORS2_EN, 1);
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#endif
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#ifdef HAL_GPIO_PIN_VDD_3V3_SENSORS3_EN
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palWriteLine(HAL_GPIO_PIN_VDD_3V3_SENSORS3_EN, 1);
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#endif
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#ifdef HAL_GPIO_PIN_VDD_3V3_SENSORS4_EN
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palWriteLine(HAL_GPIO_PIN_VDD_3V3_SENSORS4_EN, 1);
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#endif
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#ifdef HAL_GPIO_PIN_nVDD_3V3_SD_CARD_EN
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// the TBS-Colibri-F7 needs PG7 low for SD card
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palWriteLine(HAL_GPIO_PIN_nVDD_3V3_SD_CARD_EN, 0);
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#endif
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#ifdef HAL_GPIO_PIN_VDD_3V3_SD_CARD_EN
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// others need it active high
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palWriteLine(HAL_GPIO_PIN_VDD_3V3_SD_CARD_EN, 1);
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#endif
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#ifdef HAL_GPIO_PIN_VDD_3V5_LTE_EN
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palWriteLine(HAL_GPIO_PIN_VDD_3V5_LTE_EN, 1);
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#endif
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for (i=0; i<20; i++) {
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// give 20ms for sensors to settle
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chThdSleep(chTimeMS2I(1));
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}
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#endif
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}
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32F4) || defined(STM32F3) || defined(STM32G4) || defined(STM32L4)
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/*
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read mode of a pin. This allows a pin config to be read, changed and
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then written back
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*/
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iomode_t palReadLineMode(ioline_t line)
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{
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ioportid_t port = PAL_PORT(line);
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uint8_t pad = PAL_PAD(line);
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iomode_t ret = 0;
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ret |= (port->MODER >> (pad*2)) & 0x3;
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ret |= ((port->OTYPER >> pad)&1) << 2;
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ret |= ((port->OSPEEDR >> (pad*2))&3) << 3;
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ret |= ((port->PUPDR >> (pad*2))&3) << 5;
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if (pad < 8) {
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ret |= ((port->AFRL >> (pad*4))&0xF) << 7;
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} else {
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ret |= ((port->AFRH >> ((pad-8)*4))&0xF) << 7;
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}
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return ret;
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}
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/*
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set pin as pullup, pulldown or floating
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*/
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void palLineSetPushPull(ioline_t line, enum PalPushPull pp)
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{
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ioportid_t port = PAL_PORT(line);
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uint8_t pad = PAL_PAD(line);
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port->PUPDR = (port->PUPDR & ~(3<<(pad*2))) | (pp<<(pad*2));
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}
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#endif // F7, H7, F4
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void stm32_cacheBufferInvalidate(const void *p, size_t size)
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{
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cacheBufferInvalidate(p, size);
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}
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void stm32_cacheBufferFlush(const void *p, size_t size)
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{
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cacheBufferFlush(p, size);
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}
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|
|
|
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#ifdef HAL_GPIO_PIN_FAULT
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/*
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optional support for hard-fault debugging using soft-serial output to a pin
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To use this setup a pin like this:
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Pxx FAULT OUTPUT HIGH
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for some pin Pxx
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On a STM32F405 the baudrate will be around 42kBaud. Use the
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auto-baud function on your logic analyser to decode
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*/
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/*
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send one bit out a debug line
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*/
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static void fault_send_bit(ioline_t line, uint8_t b)
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{
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palWriteLine(line, b);
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for (uint32_t i=0; i<1000; i++) {
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palWriteLine(line, b);
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}
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}
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|
|
/*
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send a byte out a debug line
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*/
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static void fault_send_byte(ioline_t line, uint8_t b)
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{
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fault_send_bit(line, 0); // start bit
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for (uint8_t i=0; i<8; i++) {
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uint8_t bit = (b & (1U<<i))?1:0;
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fault_send_bit(line, bit);
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}
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fault_send_bit(line, 1); // stop bit
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}
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|
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/*
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send a string out a debug line
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*/
|
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static void fault_send_string(const char *str)
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{
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while (*str) {
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fault_send_byte(HAL_GPIO_PIN_FAULT, (uint8_t)*str++);
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}
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fault_send_byte(HAL_GPIO_PIN_FAULT, (uint8_t)'\n');
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}
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|
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void fault_printf(const char *fmt, ...)
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{
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static char buffer[100];
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va_list ap;
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va_start(ap, fmt);
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vsnprintf(buffer, sizeof(buffer), fmt, ap);
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va_end(ap);
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fault_send_string(buffer);
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}
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#endif // HAL_GPIO_PIN_HARDFAULT
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|
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void system_halt_hook(void)
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{
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#ifdef HAL_GPIO_PIN_FAULT
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// optionally print the message on a fault pin
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while (true) {
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fault_printf("PANIC:%s\n", currcore->dbg.panic_msg);
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fault_printf("RA0:0x%08x\n", __builtin_return_address(0));
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}
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#endif
|
|
}
|
|
|
|
// hook for stack overflow
|
|
void stack_overflow(thread_t *tp)
|
|
{
|
|
#if !defined(HAL_BOOTLOADER_BUILD) && !defined(IOMCU_FW)
|
|
extern void AP_stack_overflow(const char *thread_name);
|
|
AP_stack_overflow(tp->name);
|
|
// if we get here then we are armed and got a stack overflow. We
|
|
// will report an internal error and keep trying to fly. We are
|
|
// quite likely to crash anyway due to memory corruption. The
|
|
// watchdog data should record the thread name and fault type
|
|
#else
|
|
(void)tp;
|
|
#endif
|
|
}
|
|
|
|
#if CH_DBG_ENABLE_STACK_CHECK == TRUE
|
|
/*
|
|
check how much stack is free given a stack base. Assumes the fill
|
|
byte is 0x55
|
|
*/
|
|
uint32_t stack_free(void *stack_base)
|
|
{
|
|
const uint32_t *p = (uint32_t *)stack_base;
|
|
const uint32_t canary_word = 0x55555555;
|
|
while (*p == canary_word) {
|
|
p++;
|
|
}
|
|
return ((uint32_t)p) - (uint32_t)stack_base;
|
|
}
|
|
#endif
|
|
|
|
#if HAL_USE_HW_RNG && defined(RNG)
|
|
static bool stm32_rand_generate(uint32_t *val)
|
|
{
|
|
uint32_t error_bits = 0;
|
|
error_bits = RNG_SR_SEIS | RNG_SR_CEIS;
|
|
/* Check for error flags and if data is ready. */
|
|
if (((RNG->SR & error_bits) == 0) && ((RNG->SR & RNG_SR_DRDY) == RNG_SR_DRDY)) {
|
|
*val = RNG->DR;
|
|
} else {
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool stm32_rand_generate_blocking(unsigned char* output, unsigned int sz, uint32_t timeout_us)
|
|
{
|
|
unsigned int i = 0;
|
|
uint32_t run_until = hrt_micros32() + timeout_us;
|
|
uint32_t val;
|
|
while ((i < sz) && (hrt_micros32() < run_until)) {
|
|
/* If not aligned or there is odd/remainder */
|
|
if( (i + sizeof(uint32_t)) > sz ||
|
|
((uint32_t)&output[i] % sizeof(uint32_t)) != 0) {
|
|
/* Single byte at a time */
|
|
if (stm32_rand_generate(&val)) {
|
|
output[i] = val;
|
|
i++;
|
|
}
|
|
} else {
|
|
/* Use native 32 bit copy instruction */
|
|
if (stm32_rand_generate((uint32_t*)&output[i])) {
|
|
i += sizeof(uint32_t);
|
|
}
|
|
}
|
|
}
|
|
return i >= sz;
|
|
}
|
|
|
|
unsigned int stm32_rand_generate_nonblocking(unsigned char* output, unsigned int sz)
|
|
{
|
|
if ((RNG->SR & RNG_SR_DRDY) != RNG_SR_DRDY) {
|
|
return false;
|
|
}
|
|
unsigned int i = 0;
|
|
uint32_t val;
|
|
while (i < sz) {
|
|
/* If not aligned or there is odd/remainder */
|
|
if( (i + sizeof(uint32_t)) > sz ||
|
|
((uint32_t)&output[i] % sizeof(uint32_t)) != 0) {
|
|
/* Single byte at a time */
|
|
if (stm32_rand_generate(&val)) {
|
|
output[i] = val;
|
|
i++;
|
|
} else {
|
|
break;
|
|
}
|
|
} else {
|
|
/* Use native 32 bit copy instruction */
|
|
if (stm32_rand_generate((uint32_t*)&output[i])) {
|
|
i += sizeof(uint32_t);
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
return i;
|
|
}
|
|
|
|
#endif // #if HAL_USE_HW_RNG && defined(RNG)
|
|
|
|
/*
|
|
see if we should limit flash to 1M on devices with older revisions of STM32F427
|
|
*/
|
|
#ifdef STM32F427xx
|
|
bool check_limit_flash_1M(void)
|
|
{
|
|
const uint16_t revid = (*(uint32_t *)DBGMCU_BASE) >> 16;
|
|
static const uint16_t badrevs[4] = { 0x1000, 0x1001, 0x1003, 0x1007 };
|
|
for (uint8_t i=0; i<4; i++) {
|
|
if (revid == badrevs[i]) {
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
#endif
|