mirror of
https://github.com/ArduPilot/ardupilot
synced 2025-02-02 05:58:30 -04:00
0905ffa438
* Use clang to verify no unused files * Add a topic table to prepare for code generating interfaces * Generated IDL's to to a generated directory in build * Use black to format python files * Populate a ROS time maessage with Linux epoch time for ROS time * Add workarounds for PoseStamped and TwistStamped with manual mods to IDL Signed-off-by: Ryan Friedman <ryanfriedman5410+github@gmail.com> Co-authored-by: Rhys Mainwaring <rhys.mainwaring@me.com> Co-authored-by: Arsh Pratap <arshpratapofficial@gmail.com> Co-authored-by: Andrew Tridgell <andrew@tridgell.net> Co-authored-by: Russ Webber <russ@rw.id.au> Co-authored-by: Peter Barker <pb-gh@barker.dropbear.id.au>
110 lines
3.6 KiB
Python
110 lines
3.6 KiB
Python
#!/usr/bin/env python
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# encoding: utf-8
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import os
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def configure(cfg):
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extra_src = [
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'modules/Micro-XRCE-DDS-Client/src/c/core/session/stream/*.c',
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'modules/Micro-XRCE-DDS-Client/src/c/core/session/*.c',
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'modules/Micro-XRCE-DDS-Client/src/c/core/serialization/*.c',
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'modules/Micro-XRCE-DDS-Client/src/c/util/*.c',
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'modules/Micro-XRCE-DDS-Client/src/c/profile/transport/serial/serial_transport.c',
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'modules/Micro-XRCE-DDS-Client/src/c/profile/transport/stream_framing/stream_framing_protocol.c',
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'modules/Micro-CDR/src/c/types/*.c',
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'modules/Micro-CDR/src/c/common.c',
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]
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cfg.env.AP_LIB_EXTRA_SOURCES['AP_DDS'] = []
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for pattern in extra_src:
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s = cfg.srcnode.ant_glob(pattern, dir=False, src=True)
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for x in s:
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cfg.env.AP_LIB_EXTRA_SOURCES['AP_DDS'].append(str(x))
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extra_src_inc = [
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'modules/Micro-XRCE-DDS-Client/include',
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'modules/Micro-XRCE-DDS-Client/include/uxr/client',
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'modules/Micro-CDR/src/c',
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'modules/Micro-CDR/include',
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'modules/Micro-CDR/include/ucdr',
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]
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for inc in extra_src_inc:
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cfg.env.INCLUDES += [str(cfg.srcnode.make_node(inc))]
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# auto update submodules
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cfg.env.append_value('GIT_SUBMODULES', 'Micro-XRCE-DDS-Client')
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cfg.env.append_value('GIT_SUBMODULES', 'Micro-CDR')
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def build(bld):
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config_h_in = [
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'modules/Micro-XRCE-DDS-Client/include/uxr/client/config.h.in',
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'modules/Micro-CDR/include/ucdr/config.h.in',
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]
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config_h_in_nodes = [bld.srcnode.make_node(h) for h in config_h_in]
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config_h_nodes = [bld.bldnode.find_or_declare(h[:-3]) for h in config_h_in]
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gen_path = "libraries/AP_DDS"
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extra_bld_inc = [
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'modules/Micro-CDR/include',
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'modules/Micro-XRCE-DDS-Client/include',
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gen_path,
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]
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for inc in extra_bld_inc:
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bld.env.INCLUDES += [bld.bldnode.find_or_declare(inc).abspath()]
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for i in range(len(config_h_nodes)):
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print("building %s" % config_h_nodes[i].abspath())
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bld(
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# build config.h file
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source=config_h_in_nodes[i],
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target=config_h_nodes[i],
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rule="%s %s/%s %s %s"
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% (
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bld.env.get_flat('PYTHON'),
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bld.env.SRCROOT,
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"libraries/AP_DDS/gen_config_h.py",
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config_h_in_nodes[i].abspath(),
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config_h_nodes[i].abspath(),
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),
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group='dynamic_sources',
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)
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# temporary whitelist while include issue is sorted out
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whitelist = [
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'BatteryState.idl',
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'Duration.idl',
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'Header.idl',
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'NavSatFix.idl',
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'NavSatStatus.idl',
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'Point.idl',
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'Pose.idl',
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'PoseStamped.idl',
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'Quaternion.idl',
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'Time.idl',
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'Twist.idl',
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'TwistStamped.idl',
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'Vector3.idl',
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]
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idl_files = bld.srcnode.ant_glob('libraries/AP_DDS/Idl/**/*.idl')
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for idl in idl_files:
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b = os.path.basename(idl.abspath())
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if not b in whitelist:
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continue
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gen_h = b.replace('.idl', '.h')
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gen_c = b.replace('.idl', '.c')
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gen = [
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bld.bldnode.find_or_declare(os.path.join(gen_path, "generated", gen_h)),
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bld.bldnode.find_or_declare(os.path.join(gen_path, "generated", gen_c)),
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]
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bld(
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# build IDL file
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source=idl,
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target=gen,
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rule=f"{bld.env.MICROXRCEDDSGEN[0]} -replace -d {os.path.join(gen_path, 'generated')} {idl}",
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group='dynamic_sources',
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)
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bld.env.AP_LIB_EXTRA_SOURCES['AP_DDS'] += [os.path.join('generated', gen_c)]
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