mirror of https://github.com/ArduPilot/ardupilot
152 lines
3.6 KiB
C
152 lines
3.6 KiB
C
/*
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independent watchdog support
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*/
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#include "hal.h"
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#include "watchdog.h"
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#include "stm32_util.h"
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#ifndef IWDG_BASE
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#if defined(STM32H7)
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#define IWDG_BASE 0x58004800
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#elif defined(STM32F7) || defined(STM32F4)
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#define IWDG_BASE 0x40003000
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#elif defined(STM32F1) || defined(STM32F3)
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#define IWDG_BASE 0x40003000
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#else
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#error "Unsupported IWDG MCU config"
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#endif
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#endif
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#ifndef RCC_BASE
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#error "Unsupported IWDG RCC MCU config"
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#endif
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/*
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define for controlling how long the watchdog is set for.
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*/
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#ifndef STM32_WDG_TIMEOUT_MS
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#define STM32_WDG_TIMEOUT_MS 2048
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#endif
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#if STM32_WDG_TIMEOUT_MS > 4096 || STM32_WDG_TIMEOUT_MS < 20
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#error "Watchdog timeout out of range"
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#endif
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/*
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defines for working out if the reset was from the watchdog
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*/
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#if defined(STM32H7)
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#define WDG_RESET_STATUS (*(__IO uint32_t *)(RCC_BASE + 0xD0))
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#define WDG_RESET_CLEAR (1U<<16)
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#define WDG_RESET_IS_IWDG (1U<<26)
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#define WDG_RESET_IS_SFT (1U<<24)
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#elif defined(STM32F7) || defined(STM32F4)
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#define WDG_RESET_STATUS (*(__IO uint32_t *)(RCC_BASE + 0x74))
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#define WDG_RESET_CLEAR (1U<<24)
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#define WDG_RESET_IS_IWDG (1U<<29)
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#define WDG_RESET_IS_SFT (1U<<28)
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#elif defined(STM32F1) || defined(STM32F3)
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#define WDG_RESET_STATUS (*(__IO uint32_t *)(RCC_BASE + 0x24))
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#define WDG_RESET_CLEAR (1U<<24)
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#define WDG_RESET_IS_IWDG (1U<<29)
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#define WDG_RESET_IS_SFT (1U<<28)
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#elif defined(STM32G4) || defined(STM32L4) || defined(STM32L4PLUS)
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#define WDG_RESET_STATUS (*(__IO uint32_t *)(RCC_BASE + 0x94))
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#define WDG_RESET_CLEAR (1U<<23)
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#define WDG_RESET_IS_IWDG (1U<<29)
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#define WDG_RESET_IS_SFT (1U<<28)
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#else
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#error "Unsupported IWDG MCU config"
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#endif
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typedef struct
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{
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__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
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__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
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__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
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__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
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__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
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} IWDG_Regs;
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#define IWDGD (*(IWDG_Regs *)(IWDG_BASE))
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static uint32_t reset_reason;
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static bool watchdog_enabled;
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/*
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setup the watchdog
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*/
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void stm32_watchdog_init(void)
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{
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// setup the watchdog timeout
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// t = 4 * 2^PR * (RLR+1) / 32KHz
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IWDGD.KR = 0x5555;
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IWDGD.PR = 3; // changing this would change the definition of STM32_WDG_TIMEOUT_MS
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IWDGD.RLR = STM32_WDG_TIMEOUT_MS - 1;
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IWDGD.KR = 0xCCCC;
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watchdog_enabled = true;
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}
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/*
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pat the dog, to prevent a reset. If not called for STM32_WDG_TIMEOUT_MS
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after stm32_watchdog_init() then MCU will reset
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*/
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void stm32_watchdog_pat(void)
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{
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if (watchdog_enabled) {
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IWDGD.KR = 0xAAAA;
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}
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}
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/*
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save reason code for reset
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*/
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void stm32_watchdog_save_reason(void)
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{
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if (reset_reason == 0) {
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reset_reason = WDG_RESET_STATUS;
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}
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}
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/*
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clear reason code for reset
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*/
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void stm32_watchdog_clear_reason(void)
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{
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WDG_RESET_STATUS = WDG_RESET_CLEAR;
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}
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/*
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return true if reboot was from a watchdog reset
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*/
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bool stm32_was_watchdog_reset(void)
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{
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stm32_watchdog_save_reason();
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return (reset_reason & WDG_RESET_IS_IWDG) != 0;
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}
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/*
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return true if reboot was from a software reset
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*/
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bool stm32_was_software_reset(void)
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{
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stm32_watchdog_save_reason();
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return (reset_reason & WDG_RESET_IS_SFT) != 0;
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}
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/*
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save persistent watchdog data
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*/
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void stm32_watchdog_save(const uint32_t *data, uint32_t nwords)
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{
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set_rtc_backup(1, data, nwords);
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}
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/*
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load persistent watchdog data
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*/
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void stm32_watchdog_load(uint32_t *data, uint32_t nwords)
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{
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get_rtc_backup(1, data, nwords);
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}
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