Many of our SPI and I2C sensors define the protocol of setting the most
significant bit of the register address in order to perform a read operation.
Thus, enable the use of a "read flag" that is ORed with the register's address.
Since this is an abstraction for general devices, it's a good idea to have zero
as the default value for that flag.
While at it, add documentation to read_registers().
../../libraries/AP_HAL_Linux/Perf.cpp: In member function ‘void Linux::Perf::_debug_counters()’:
../../libraries/AP_HAL_Linux/Perf.cpp:85:36: warning: format ‘%llu’ expects argument of type ‘long long unsigned int’, but argument 4 has type ‘uint64_t {aka long unsigned int}’ [-Wformat=]
c.name, c.count);
^
this reduces elevator control when rolled over hard in fixed
wing. Using the elevator when on the side just caused earth frame yaw
and is counter productive. It can also prevent some aircraft from
recovering from inverted flight.
That fixed compilation issues and seems more semantically correct. Using array
of length 0 fails compilation because of -Werror=array-bounds in GCC 6.1.
That fixed compilation issues and seems more semantically correct. Using array
of length 0 fails compilation because of -Werror=array-bounds in GCC 6.1.
Add DEFINE prefix, since this macro is defining these operators and
remove the parameter since we will always use it to access a
union/struct as a byte array.
Test code for integration with another thread to pull data from internal
perf counters. Since we are using the timer thread here, there's no
retry mechanism and we only print that data can be corrupted.
Instead of creating a new object Perf_Lttng copying the necessaries
fields, just make a tighter integration with the internal perf counters
and re-use the same fields.
The idea is to leave the internal perf enabled all the time, like it is
in PX4, and then allow the integration with lttng on top. Next step
would be to runtime enable/disable only the perf counters we are
interested in.
This also changes the structure so it's easy to allow another thread to
pull data from the Perf object. A rw lock protects from addition of new
counters and an atomic unsigned int allows other threads to do a
lockless copy of the data.
In order for this to work the allocation was changed to use a single
memory pool instead of returning a calloc'ed data for each perf counter.
Since most of our counters are of ' elapsed' type, don't bother using a
smaller struct for the 'count' type
