this avoids an issue with the ChibiOS 20.3 virtual timer
implementation that can result in a scheduling slip equal to the
system timer period.
Andy has been suggesting this change for a while. I resisted it as I
thought it would impact on soft-serial parsing, but it turns out it
doesn't.
Fixes issue #18383
with the new ChibiOS revision we were configuring for newer revisions
of the H7, which meant that we changed the ADC config. This broke ADC
readings on revX and revY H7 MCUs.
This PR fixes it in two ways:
1) change ChibiOS config to assume XY config chips
2) use 16 bit ADC for H7, which means the chip rev doesn't matter,
and also gives us 16x the resolution for ADC readinga, so we can
read smaller voltage and current values
this takes better advantage of the new UART code. Log download over
USB gets to 730 kbyte/s. For comparison, with the 4.0 code on the same
H7 we get about 300 kbyte/s
this gains about 20k of RAM, and has almost no impact on log download
speed at 921600 on a F427. The improved threading means we can afford
to have smaller buffers
refactor rcout into separate thread and process all dshot requests there
move uart DMA completion to event model
process dshot locks in strick reverse order when unlocking
convert Shared_DMA to use mutexes
move UART transmit to a thread-per-uart
do blocking UART DMA transactions
do blocking dshot DMA transactions
trim stack sizes
cancel dma transactions on dshot when timeout occurs
support contention stats on blocking locking
move thread supression into chibios_hwdef.py
invalidate DMA bounce buffer correctly
separate UART initialisation into two halves
cleanup UART transaction timeouts
add @SYS/uarts.txt
move half-duplex handling to TX thread
correct thread statistics after use of ExpandingString
set unbuffered TX thread priority owner + 1
correctly unlock serial_led_send()
don't share IMU RX on KakuteF7Mini
observe dshot pulse time more accurately.
set TRBUFF bit for UART DMA transfers
deal with UART DMA timeouts correctly
don't deadlock on reverse ordered DMA locks
change PORT_INT_REQUIRED_STACK to 128
Adjust SRAM1+SRAM2 to 256k as describe in the H743 reference manual
Provide access to mem_info() information
Co-authored-by: Andrew Tridgell <andrew@tridgell.net>
the STM32H7 has 64k of ITCM memory at address zero. We allow
allocation of everything except the first 1024 bytes. This checks for
those reserved bytes being overwritte, which would indicate a write to
nullptr
Andrew Tridgell
bugobliterator
Michael Oborne
Andy Piper
Iampete1
pkocmoud