3 Commits

Author	SHA1	Message	Date
Andrew Tridgell	7ecf8981b9	SITL: added dummy SPI and make RCInput 50Hz	2012-12-20 14:52:34 +11:00
Andrew Tridgell	e020694c03	SITL: fixed build of apm1/apm2 target	2012-12-20 14:52:34 +11:00
Andrew Tridgell	0c9d37e2ee	SITL: added RCInput and RCOutput	2012-12-20 14:52:33 +11:00