3 Commits

Author	SHA1	Message	Date
Andrew Tridgell	06a8aef998	HAL_ChibiOS: switched G4 FDCAN clock to 80MHz ... this requires main CPU clock at 160 MHz instead of 168 MHz	2024-01-25 11:44:44 +11:00
Andrew Tridgell	96518c9eda	HAL_ChibiOS: added CPU defines to hwdef ... needed for checks like defined(STM32F1)	2022-02-22 12:13:19 +11:00
Andrew Tridgell	4fce1ae092	HAL_ChibiOS: added G491 support	2021-07-30 10:20:52 +10:00