Mirror/ardupilot
5
0
Fork 0
mirror of https://github.com/ArduPilot/ardupilot synced 2025-01-22 00:28:30 -04:00
Code Issues Packages Projects Releases Wiki Activity

AP_HAL_ChibiOS: use STM32_FLASH_NBANKS for flash actions

Browse Source
This commit is contained in:
Andy Piper 2023-04-20 12:04:24 +01:00 committed by Andrew Tridgell
parent 5b43926d0a
commit ff1661a8de
1 changed files with 22 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
libraries/AP_HAL_ChibiOS/hwdef/common/flash.c
View File

@ -118,6 +118,10 @@ static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(32), KB(32), KB(32
#else
#error "BOARD_FLASH_SIZE invalid"
#endif
#elif defined(STM32H730xx) || defined(STM32H750xx)
#define STM32_FLASH_NPAGES 1
#define STM32_FLASH_NBANKS 1
#define STM32_FLASH_FIXED_PAGE_SIZE 128
#elif defined(STM32H7)
#define STM32_FLASH_NPAGES (BOARD_FLASH_SIZE / 128)
#define STM32_FLASH_FIXED_PAGE_SIZE 128
@ -143,6 +147,10 @@ static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(32), KB(32), KB(32
#error "Unsupported processor for flash.c"
#endif
#ifndef STM32_FLASH_NBANKS
#define STM32_FLASH_NBANKS 2
#endif
#if defined(__GNUC__) && __GNUC__ >= 6
#ifdef STORAGE_FLASH_PAGE
static_assert(STORAGE_FLASH_PAGE < STM32_FLASH_NPAGES,
@ -207,7 +215,7 @@ static void stm32_flash_wait_idle(void)
__DSB();
#if defined(STM32H7)
while ((FLASH->SR1 & (FLASH_SR_BSY|FLASH_SR_QW|FLASH_SR_WBNE))
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
|| (FLASH->SR2 & (FLASH_SR_BSY|FLASH_SR_QW|FLASH_SR_WBNE))
#endif
) {
@ -224,7 +232,7 @@ static void stm32_flash_clear_errors(void)
{
#if defined(STM32H7)
FLASH->CCR1 = ~0;
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
FLASH->CCR2 = ~0;
#endif
#else
@ -245,7 +253,7 @@ static void stm32_flash_unlock(void)
FLASH->KEYR1 = FLASH_KEY1;
FLASH->KEYR1 = FLASH_KEY2;
}
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
if (FLASH->CR2 & FLASH_CR_LOCK) {
/* Unlock sequence */
FLASH->KEYR2 = FLASH_KEY1;
@ -275,14 +283,14 @@ void stm32_flash_lock(void)
if (FLASH->SR1 & FLASH_SR_QW) {
FLASH->CR1 |= FLASH_CR_FW;
}
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
if (FLASH->SR2 & FLASH_SR_QW) {
FLASH->CR2 |= FLASH_CR_FW;
}
#endif
stm32_flash_wait_idle();
FLASH->CR1 |= FLASH_CR_LOCK;
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
FLASH->CR2 |= FLASH_CR_LOCK;
#endif
#else
@ -448,7 +456,7 @@ bool stm32_flash_erasepage(uint32_t page)
FLASH->CR1 |= FLASH_CR_START;
while (FLASH->SR1 & FLASH_SR_QW) ;
}
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
else {
// second bank
FLASH->SR2 = ~0;
@ -537,7 +545,7 @@ static bool stm32h7_flash_write32(uint32_t addr, const void *buf)
volatile uint32_t *CR = &FLASH->CR1;
volatile uint32_t *CCR = &FLASH->CCR1;
volatile uint32_t *SR = &FLASH->SR1;
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
if (addr - STM32_FLASH_BASE >= 8 * STM32_FLASH_FIXED_PAGE_SIZE * 1024) {
CR = &FLASH->CR2;
CCR = &FLASH->CCR2;
@ -891,7 +899,7 @@ void stm32_flash_protect_flash(bool bootloader, bool protect)
(void)protect;
#if defined(STM32H7) && HAL_FLASH_PROTECTION
uint32_t prg1 = FLASH->WPSN_CUR1;
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
uint32_t prg2 = FLASH->WPSN_CUR2;
#endif
#ifndef STORAGE_FLASH_PAGE
@ -917,7 +925,7 @@ void stm32_flash_protect_flash(bool bootloader, bool protect)
prg1 |= 1U<<i;
}
}
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
for (uint32_t i = 0; i < 8; i++) {
if (i+8 != storage_page && i+8 != storage_page+1 && protect) {
prg2 &= ~(1U<<i);
@ -930,7 +938,7 @@ void stm32_flash_protect_flash(bool bootloader, bool protect)
// check if any changes to be made
if (prg1 == FLASH->WPSN_CUR1
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
&& prg2 == FLASH->WPSN_CUR2
#endif
) {
@ -942,7 +950,7 @@ void stm32_flash_protect_flash(bool bootloader, bool protect)
if (stm32_flash_unlock_options()) {
FLASH->WPSN_PRG1 = prg1;
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
FLASH->WPSN_PRG2 = prg2;
#endif
FLASH->OPTCR |= FLASH_OPTCR_OPTSTART;
@ -964,7 +972,7 @@ void stm32_flash_unprotect_flash()
stm32_flash_opt_clear_errors();
stm32_flash_clear_errors();
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
if ((FLASH->PRAR_CUR2 & 0xFFF) <= ((FLASH->PRAR_CUR2 >> 16) & 0xFFF)
|| (FLASH->SCAR_CUR2 & 0xFFF) <= ((FLASH->SCAR_CUR2 >> 16) & 0xFFF)) {
@ -1012,13 +1020,13 @@ void stm32_flash_unprotect_flash()
}
// remove write protection from banks 1&2
if ((FLASH->WPSN_CUR1 & 0xFF) != 0xFF
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
|| (FLASH->WPSN_CUR2 & 0xFF) != 0xFF
#endif
) {
if (stm32_flash_unlock_options()) {
FLASH->WPSN_PRG1 = 0xFF;
#if !defined(STM32H730xx) && !defined(STM32H750xx)
#if STM32_FLASH_NBANKS > 1
FLASH->WPSN_PRG2 = 0xFF;
#endif
FLASH->OPTCR |= FLASH_OPTCR_OPTSTART;