mirror of https://github.com/ArduPilot/ardupilot
Tools: add unified device tree overlay to load all requisites
no more loading multiple capes to enable pru, spi, pwm etc. Steps to load the cape during boot also added.
This commit is contained in:
bugobliterator
Andrew Tridgell
parent
c9be610dca
commit
fdf916025a
Binary file not shown.
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@ -0,0 +1,399 @@
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/*
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* Copyright (C) 2013 Pantelis Antoniou <panto@antoniou-consulting.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/plugin/;
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/ {
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compatible = "ti,beaglebone", "ti,beaglebone-black";
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/* identification */
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part-number = "BB-PXF-01";
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version = "00A0";
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/* state the resources this cape uses */
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exclusive-use =
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/* the pin header uses */
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/* PRU */
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"P8.11", /* pru0: pr1_pru0_pru_r30_15 */
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"P8.12", /* pru0: pr1_pru0_pru_r30_14 */
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"P8.15", /* pru0: pr1_pru0_pru_r31_15*/
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"P8.16", /* pru0: pr1_pru0_pru_r31_14*/
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"P9.25", /* pru0: pr1_pru0_pru_r30_7 */
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"P9.41", /* pru0: pr1_pru0_pru_r30_6 */
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"P8.27", /* pru1: pr1_pru1_pru_r30_8 */
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"P8.28", /* pru1: pr1_pru1_pru_r30_10 */
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"P8.29", /* pru1: pr1_pru1_pru_r30_9 */
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"P8.30", /* pru1: pr1_pru1_pru_r30_11 */
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"P8.39", /* pru1: pr1_pru1_pru_r30_6 */
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"P8.40", /* pru1: pr1_pru1_pru_r30_7 */
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"P8.41", /* pru1: pr1_pru1_pru_r30_4 */
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"P8.42", /* pru1: pr1_pru1_pru_r30_5 */
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"P8.43", /* pru1: pr1_pru1_pru_r30_2 */
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"P8.44", /* pru1: pr1_pru1_pru_r30_3 */
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"P8.45", /* pru1: pr1_pru1_pru_r30_0 */
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"P8.46", /* pru1: pr1_pru1_pru_r30_1 */
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/* SPI0 */
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"P9.22", /* SPI0_SCLK */
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"P9.21", /* SPI0_MOSI */
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"P9.18", /* SPI0_MISO */
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"P9.17", /* LSM9DSO_AM CS */
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"P8.9", /* LSM9DSO_G CS */
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/* SPI1 */
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"P9.31", /* SPI1_SCLK */
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"P9.29", /* SPI1_MOSI */
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"P9.30", /* SPI1_MISO */
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"P9.42", /* MS5611 CS */
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"P9.28", /* MPU6000 CS */
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"P9.23", /* MPU9250 CS */
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"P8.12", /* FRAM CS */
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/* Buzzer PWM */
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"P8.36", /* pwm: ehrpwm1A */
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/* the hardware IP uses */
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"pru0",
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"pru1",
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"spi0",
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"spi1",
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"ehrpwm1A";
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fragment@0 {
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target = <&am33xx_pinmux>;
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__overlay__ {
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pru_gpio_pins: pinmux_pru_gpio_pins {
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pinctrl-single,pins = <
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0x1a4 0x0f /* P9 27 GPIO3_19: mcasp0_fsr.gpio3[19] | MODE7 | OUTPUT */
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>;
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};
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pru_pru_pins: pinmux_pru_pru_pins {
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pinctrl-single,pins = <
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0x034 0x26 /* gpmc_ad13.pr1_pru0_pru_r30_15, MODE6 | OUTPUT | PRU */
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0x030 0x26 /* gpmc_ad12.pr1_pru0_pru_r30_14, MODE6 | OUTPUT | PRU */
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0x03c 0x2e /* gpmc_ad15.pr1_pru0_pru_r30_15, MODE 6 | INPUT | PRU */
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0x038 0x2e /* gpmc_ad14.pr1_pru0_pru_r30_14, MODE 6 | INPUT | PRU */
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0x1ac 0x25 /* mcasp0_ahclkx.pr1_pru0_pru_r30_7, MODE5 | OUTPUT | PRU */
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0x1a8 0x25 /* mcasp0_axr1.pr1_pru0_pru_r30_6, MODE5 | OUTPUT | PRU */
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0x0e0 0x25 /* lcd_vsync.pr1_pru1_pru_r30_8, MODE5 | OUTPUT | PRU */
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0x0e8 0x25 /* lcd_pclk.pr1_pru1_pru_r30_10, MODE5 | OUTPUT | PRU */
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0x0e4 0x25 /* lcd_hsync.pr1_pru1_pru_r30_9, MODE5 | OUTPUT | PRU */
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0x0ec 0x25 /* lcd_ac_bias_en.pr1_pru1_pru_r30_11, MODE5 | OUTPUT | PRU */
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0x0b8 0x25 /* pr1_pru1_pru_r30_6, MODE5 | OUTPUT | PRU */
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0x0bc 0x25 /* lcd_data7.pr1_pru1_pru_r30_7, MODE5 | OUTPUT | PRU */
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0x0b0 0x25 /* lcd_data4.pr1_pru1_pru_r30_4, MODE5 | OUTPUT | PRU */
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0x0b4 0x25 /* lcd_data5.pr1_pru1_pru_r30_5, MODE5 | OUTPUT | PRU */
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0x0a8 0x25 /* pr1_pru1_pru_r31_2, MODE5 | OUTPUT | PRU */
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0x0ac 0x25 /* lcd_data3.pr1_pru1_pru_r30_3, MODE5 | OUTPUT | PRU */
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0x0a0 0x25 /* lcd_data0.pr1_pru1_pru_r30_0, MODE5 | OUTPUT | PRU */
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0x0a4 0x25 /* lcd_data1.pr1_pru1_pru_r30_1, MODE5 | OUTPUT | PRU */
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>;
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};
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spi0_pins_s0: spi0_pins_s0 {
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pinctrl-single,pins = <
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0x150 0x30 /* spi0_sclk, SPI0_SCLK P9_22 */
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0x154 0x10 /* spi0_d0, SPI0_MOSI P9_21 */
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0x158 0x30 /* spi0_d1, SPI0_MISO P9_18 */
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/* setup a dummy CS for the SPI driver to use, then
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setup pin modes for the two real CS lines to
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set them pull-up */
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0x054 0x07 /* led pin, dummy CS */
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0x15C 0x37 /* LSM9DSO_AM CS P9_17 */
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0x09C 0x37 /* LSM9DSO_G CS P8_9 */
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>;
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};
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spi1_pins_s0: spi1_pins_s0 {
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pinctrl-single,pins = <
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0x190 0x33 /* mcasp0_aclkx.spi1_sclk, SPI1_SCLK P9_31 */
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0x194 0x13 /* mcasp0_fsx.spi1_d0, SPI1_MOSI P9_29 */
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0x198 0x33 /* mcasp0_axr0.spi1_d1, SPI1_MISO P9_30 */
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/* setup a dummy CS for the SPI driver to use, then
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setup pin modes for the four real CS lines to
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set them pull-up */
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0x058 0x07 /* dummy CS */
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0x164 0x37 /* P9_42 MS5611 CS */
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0x19C 0x37 /* P9_28 MPU6000 CS */
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0x044 0x37 /* P9_23 MPU9250 CS */
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0x030 0x37 /* P8_12 FRAM CS */
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>;
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};
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pwm_P8_36: pinmux_pwm_P8_36_pins {
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pinctrl-single,pins = <
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0x0C8 0x02 /* P8_36 (ZCZ ball U3) | MODE 2 */
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>;
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};
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};
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};
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fragment@2 {
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target = <&spi0>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins_s0>;
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ti,pindir-d0-out-d1-in = <1>;
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spidev@0 {
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spi-max-frequency = <24000000>;
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reg = <0>;
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compatible = "linux,spidev";
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};
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};
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};
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fragment@3{
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target = <&spi1>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins_s0>;
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ti,pindir-d0-out-d1-in = <1>;
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spidev@1 {
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spi-max-frequency = <24000000>;
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reg = <0>;
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compatible = "linux,spidev";
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};
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};
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};
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fragment@4 {
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target = <&epwmss1>;
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__overlay__ {
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status = "okay";
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};
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};
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fragment@5 {
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target = <&ehrpwm1>;
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__overlay__ {
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status = "okay";
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};
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};
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fragment@6 {
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target = <&ocp>;
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__overlay__ {
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pwm_test_P8_36 {
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compatible = "pwm_test";
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pwms = <&ehrpwm1 0 500000 1>;
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pwm-names = "PWM_P8_36";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_P8_36>;
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enabled = <1>;
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duty = <0>;
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status = "okay";
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};
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};
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};
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fragment@7 {
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target = <&ocp>;
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__overlay__ {
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/* avoid stupid warning */
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#address-cells = <1>;
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#size-cells = <1>;
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prurproc {
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compatible = "ti,pru-rproc";
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pinctrl-names = "default";
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pinctrl-0 = <&pru_pru_pins>;
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reg = <0x4a300000 0x080000>;
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status = "okay";
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ti,hwmods = "pruss";
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ti,deassert-hard-reset = "pruss", "pruss";
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interrupt-parent = <&intc>;
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/* interrupts on the host */
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interrupts = <20 21 22 23 24 25 26 27>;
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/* events these interrupts map to (host interrupt) */
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events = <2 3 4 5 6 7 8 9>;
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/* PRU interrupt controller offset */
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pintc = <0x20000>;
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/* 12K Shared Data RAM global, size, local */
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pdram = <0x10000 0x03000 0x10000>;
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/*
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* SYSEVENT ids
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*
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* - PRU/ARM communication
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* PRU0_PRU1 17
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* PRU1_PRU0 18
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* PRU0_ARM 19
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* PRU1_ARM 20
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* ARM_PRU0 21
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* ARM_PRU1 22
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*
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* Full SYSEVENT list
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*
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* parity_err_intr_pend 0
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* pru0_r31_status_cnt16 1
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* pru1_r31_status_cnt16 2
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* uart_urxevt_intr_req 4
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* uart_utxevt_intr_req 5
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* uart_uint_intr_req 6
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* iep_tim_cap_cmp_pend 7
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* ecap_intr_req 15
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* pru_mst_intr[0-15]_intr_req 16-31
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* nirq 32 (UART1)
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* mcasp_x_intr_pend 33 (MCASP1)
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* mcasp_r_intr_pend 34 (MCASP1)
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* ecap_intr_intr_pend 35 (ECAP1)
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* ecap_intr_intr_pend 36 (ECAP2)
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* epwm_intr_intr_pend 37 (eHRPWM2)
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* dcan_uerr 38 (DCAN0)
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* dcan_int1 39 (DCAN0)
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* dcan_intr 40 (DCAN0)
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* POINTRPEND 41 (I2C0)
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* ecap_intr_intr_pend 42 (ECAP0)
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* epwm_intr_intr_pend 43 (eHRPWM0)
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* SINTERRUPTN 44 (McSPI0)
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* eqep_intr_intr_pend 45 (eQEP0)
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* epwm_intr_intr_pend 46 (eHRPWM1)
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* c0_misc_pend 47 3PGSW (GEMAC)
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* c0_tx_pend 48 3PGSW (GEMAC)
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* c0_rx_pend 49 3PGSW (GEMAC)
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* c0_rx_thresh_pend 50 3PGSW (GEMAC)
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* nirq 51 (UART0)
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* nirq 52 (UART2)
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* gen_intr_pend 53 (ADC_TSC)
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* mcasp_r_intr_pend 54 (McASP0)
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* mcasp_x_intr_pend 55 (McASP1)
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* pwm_trip_zone 56 (eHRPWM0/eHRPWM1/eHRP WM2)
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* POINTRPEND1 57 (GPIO0)
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* Emulation Suspend Signal 58 (Debugss)
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* initiator_sinterrupt_q_n2 59 (Mbox0 - mail_u2_irq (mailbox interrupt for pru1))
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* initiator_sinterrupt_q_n1 60 (Mbox0 - mail_u1_irq (mailbox interrupt for pru0))
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* tptc_erint_pend_po 61 (TPTC0 (EDMA))
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* tpcc_errint_pend_po 62 (TPCC (EDMA))
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* tpcc_int_pend_po1 63 (TPCC (EDMA))
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*
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* HOST interrupt ids
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*
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* PRU0 0
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* PRU1 1
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* EVTOUT0-7 2-9
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*/
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/* sysevent map to intc channel */
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sysevent-to-channel-map =
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<17 1>, /* PRU0_PRU1 -> CH1 */
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<18 0>, /* PRU1_PRU0 -> CH0 */
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<19 2>, /* PRU0_ARM -> CH2 */
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<20 3>, /* PRU1_ARM -> CH3 */
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<21 0>, /* ARM_PRU0 -> CH0 */
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<22 1>, /* ARM_PRU1 -> CH1 */
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<24 4>, /* VRING Host->PRU0 -> CH4 */
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<25 5>, /* VRING PRU0->Host -> CH5 */
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<26 6>, /* VRING Host->PRU1 -> CH6 */
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<27 7>; /* VRING PRU1->Host -> CH7 */
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/* channel to host interrupt map */
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channel-to-host-interrupt-map =
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<0 0>, /* CH0 -> PRU0 */
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<1 1>, /* CH1 -> PRU1 */
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<2 2>, /* CH2 -> EVTOUT0 */
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<3 3>, /* CH3 -> EVTOUT1 */
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<4 0>, /* CH4 -> PRU0 */
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<5 6>, /* CH5 -> EVTOUT4 */
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<6 1>, /* CH6 -> PRU1 */
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<7 7>; /* CH7 -> EVTOUT5 */
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/* indices are ARM=0, PRU0=1, PRU1=2 */
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target-to-sysevent-map =
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<0xffffffff 21 22>, /* ARM: DONTCARE, ARM_PRU0, ARM_PRU1 */
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< 19 0xffffffff 17>, /* PRU0: PRU0_ARM, DONTCARE, PRU0_PRU1 */
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< 20 18 0xffffffff>; /* PRU1: PRU1_ARM, PRU1_PRU0, DONTCARE */
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||||||
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/* both the PRUs have 200MHz frequency so period is 5ns */
|
||||||
|
clock-freq = <200000000>;
|
||||||
|
|
||||||
|
/* the linux pwms we support */
|
||||||
|
pru-pwm-channels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 21>;
|
||||||
|
/* first PRU controls the PWMs */
|
||||||
|
pru-pwm-controller = <0>;
|
||||||
|
/* the IDs of the downcalls the firmware expects for PWMs */
|
||||||
|
/* CONFIG=0, ENABLE=1, DISABLE=2 */
|
||||||
|
pru-pwm-dc-ids = <0 1 2>;
|
||||||
|
|
||||||
|
/* definition for the first PRU */
|
||||||
|
pru0 {
|
||||||
|
pru-index = <0>;
|
||||||
|
|
||||||
|
/* offset, size, local */
|
||||||
|
iram = <0x34000 0x02000 0x00000>; /* code ram (8K) */
|
||||||
|
|
||||||
|
/* offset, size, local, other */
|
||||||
|
dram = <0x00000 0x02000 0x00000 0x10000>; /* data ram (8K) */
|
||||||
|
|
||||||
|
pctrl = <0x22000>;
|
||||||
|
pdbg = <0x22400>;
|
||||||
|
|
||||||
|
firmware-elf;
|
||||||
|
firmware = "testpru0";
|
||||||
|
|
||||||
|
/* sysevents signaling ring activity (host, pru)*/
|
||||||
|
vring-sysev = <24 25>;
|
||||||
|
|
||||||
|
resource_table {
|
||||||
|
resource-table;
|
||||||
|
version = <1>;
|
||||||
|
|
||||||
|
pru0_rproc_serial: pru0_vdev_rproc_serial {
|
||||||
|
vdev-rproc-serial;
|
||||||
|
|
||||||
|
/* notification IDs are totally bogus */
|
||||||
|
/* rproc will idr_alloc anyway */
|
||||||
|
|
||||||
|
notifyid = <8>; /* <- bogus */
|
||||||
|
/* da align num notifyid */
|
||||||
|
vring-0 = <0 16 8 0>;
|
||||||
|
vring-1 = <0 16 8 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/* definition for the second PRU */
|
||||||
|
pru1 {
|
||||||
|
pru-index = <1>;
|
||||||
|
|
||||||
|
/* offset, size, local */
|
||||||
|
iram = <0x38000 0x02000 0x00000>; /* code ram (8K) */
|
||||||
|
|
||||||
|
/* offset, size, local, other */
|
||||||
|
dram = <0x02000 0x02000 0x00000 0x10000>; /* data ram (8K) */
|
||||||
|
|
||||||
|
pctrl = <0x24000>;
|
||||||
|
pdbg = <0x24400>;
|
||||||
|
|
||||||
|
firmware-elf;
|
||||||
|
firmware = "pwmpru1";
|
||||||
|
|
||||||
|
/* NOTE: no resource table, no vrings for this one */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -37,4 +37,8 @@ source ~/.bashrc
|
||||||
* To load firmware use
|
* To load firmware use
|
||||||
- `./startup.sh load` : only once after reboot it will copy overlays and firmware to `/lib/firmware/` and loads them.
|
- `./startup.sh load` : only once after reboot it will copy overlays and firmware to `/lib/firmware/` and loads them.
|
||||||
- `./startup.sh reload` : it only copies firmware to `/lib/firmware/` and reloads pru firmware.
|
- `./startup.sh reload` : it only copies firmware to `/lib/firmware/` and reloads pru firmware.
|
||||||
|
* Enable loading cape during BBB startup (no need to follow above step if you do this step once):
|
||||||
|
- `cp BB-PXF-01-00A0.dtbo /lib/firmware`
|
||||||
|
- add `cape_enable=capemgr.enable_partno=BB-PXF-01` to `/boot/uboot/uEnv.txt`
|
||||||
|
- add `CAPE=BB-PXF-01` to `/etc/default/capemgr`
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue