HAL_ChibiOS: support 12MHz crystal on L4xx MCUs

This commit is contained in:
Andrew Tridgell 2021-11-25 14:31:42 +11:00
parent afb64eb39f
commit fbadc24fca

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@ -37,6 +37,15 @@
#define STM32_PLLM_VALUE 1
#define STM32_PLLSRC STM32_PLLSRC_HSE
#elif STM32_HSECLK == 12000000U
#define STM32_HSE_ENABLED TRUE
#define STM32_HSI16_ENABLED FALSE
#define STM32_PLLM_VALUE 3
#define STM32_PLLN_VALUE 40
#define STM32_PLLSAI1N_VALUE 24
#define STM32_PLLSAI2N_VALUE 16
#define STM32_PLLSRC STM32_PLLSRC_HSE
#elif STM32_HSECLK == 16000000U
#define STM32_HSE_ENABLED TRUE
#define STM32_HSI16_ENABLED FALSE
@ -67,7 +76,9 @@
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#ifndef STM32_PLLN_VALUE
#define STM32_PLLN_VALUE 20
#endif
#define STM32_PLLPDIV_VALUE 0
#define STM32_PLLP_VALUE 7
#define STM32_PLLQ_VALUE 2
@ -79,12 +90,16 @@
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#ifndef STM32_PLLSAI1N_VALUE
#define STM32_PLLSAI1N_VALUE 12
#endif
#define STM32_PLLSAI1PDIV_VALUE 0
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 2
#define STM32_PLLSAI1R_VALUE 2
#ifndef STM32_PLLSAI2N_VALUE
#define STM32_PLLSAI2N_VALUE 8
#endif
#define STM32_PLLSAI2PDIV_VALUE 0
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2R_VALUE 2