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ChibiOS: added automatic reset of SPI peripherals on STM32 

An electrical glitch (such as shorting the SCK and MOSI pins) can
cause the SPI peripheral on a STM32F7xx to get into a state where it
receives corrupted bytes on the bus. This detects that state by
looking for unexpected bytes on the FIFO and resetting the peripheral
using the RCC
This commit is contained in:
Andrew Tridgell 2019-07-27 20:57:21 +10:00
parent 04944fa6ce
commit f840e6cd77
1 changed files with 1 additions and 1 deletions
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2
modules/ChibiOS

@ -1 +1 @@
Subproject commit 266646ea1e9a9d576339556a88a444a915405e29
Subproject commit b96e543701dd16b05e63be647f5a000cf4c7a023