AP_HAL_ChibiOS: use hardware serial inversion pins on F4 boards that support it

change mamba F405 to active high as per betaflight
This commit is contained in:
Andy Piper 2021-08-18 08:35:14 +01:00 committed by Andrew Tridgell
parent 94ed5b876f
commit e7e3b478fc
4 changed files with 8 additions and 10 deletions

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@ -74,8 +74,8 @@ SERIAL_ORDER OTG1 USART6 USART1 UART4 UART5 USART3
PB11 TIM2_CH4 TIM2 RCININT FLOAT LOW
PB10 USART3_TX USART3
# SBUS inversion control pin, active low
PB15 SBUS_INVERT OUTPUT LOW
# SBUS inversion control pin, active high
PB15 USART3_RXINV OUTPUT LOW GPIO(78) POL(1)
# for FrSky S.PORT. Has builtin inverters and diode to combine
# RX and TX onto the one pin

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@ -41,8 +41,8 @@ PA9 USART1_TX USART1 NODMA
# Alt config to allow RCIN on UART
PA10 USART1_RX USART1 NODMA ALT(1)
# SBUS inversion control pin, active low
PC0 USART1_RXINV OUTPUT HIGH GPIO(78) POL(0)
# SBUS inversion control pin, active high
PC0 USART1_RXINV OUTPUT LOW GPIO(78) POL(1)
# USART3
PB10 USART3_TX USART3

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@ -41,9 +41,6 @@ define HAL_BATT_CURR_PIN 11
define HAL_BATT_VOLT_SCALE 10.1
define HAL_BATT_CURR_SCALE 17.0
PC0 SBUS_INVERT OUTPUT LOW
# LEDs
PB5 LED_BLUE OUTPUT LOW GPIO(0)
PB6 LED_YELLOW OUTPUT LOW GPIO(1) # optional
@ -52,6 +49,8 @@ PB4 LED_RED OUTPUT LOW GPIO(2)
# GPS port
PC6 USART6_TX USART6
PC7 USART6_RX USART6
# SBUS inversion control pin, active high
PC0 USART6_RXINV OUTPUT LOW GPIO(78) POL(1)
# USART3 (SERIAL2) on flexi port in BRD_ALT_CONFIG = 3 & 4 & 5
PB10 USART3_TX USART3 ALT(3)

View File

@ -41,9 +41,6 @@ define HAL_BATT_CURR_PIN 11
define HAL_BATT_VOLT_SCALE 10.1
define HAL_BATT_CURR_SCALE 17.0
PC0 SBUS_INVERT OUTPUT LOW
# LEDs
PB5 LED_BLUE OUTPUT LOW GPIO(0)
PB6 LED_YELLOW OUTPUT LOW GPIO(1) # optional
@ -52,6 +49,8 @@ PB4 LED_RED OUTPUT LOW GPIO(2)
# GPS port disabled (PC6 used for RCIN)
#PC6 USART6_TX USART6
#PC7 USART6_RX USART6
# SBUS inversion control pin, active high
#PC0 USART6_RXINV OUTPUT LOW GPIO(78) POL(1)
# flexi port, setup as GPS
PB10 USART3_TX USART3