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https://github.com/ArduPilot/ardupilot
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HAL_ChibiOS: support SDIO 48MHz clock on F412
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@ -114,6 +114,7 @@
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#else
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#error "Unsupported F7 HSE clock"
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#endif
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#define STM32_PLLI2SQ_VALUE 4
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#else // F4
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#if HAL_EXPECTED_SYSCLOCK == 100000000
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// low frequency variants of F4, such as F412
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@ -128,24 +129,37 @@
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#define STM32_PLLN_VALUE 100
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 2
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#define STM32_PLLI2SM_VALUE 16
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#elif STM32_HSECLK == 8000000U
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#define STM32_PLLM_VALUE 4
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#define STM32_PLLN_VALUE 100
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 2
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#define STM32_PLLI2SM_VALUE 8
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#elif STM32_HSECLK == 16000000U
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#define STM32_PLLM_VALUE 8
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#define STM32_PLLN_VALUE 100
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 2
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#define STM32_PLLI2SM_VALUE 16
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#elif STM32_HSECLK == 24000000U
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#define STM32_PLLM_VALUE 12
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#define STM32_PLLN_VALUE 100
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 2
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#define STM32_PLLI2SM_VALUE 24
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#else
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#error "Unsupported F4 HSE clock"
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#endif
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// also setup 48MHz clock to allow for SDIO
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SP_VALUE 2
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PLLI2SR_VALUE 2
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#define STM32_PLLI2SSRC STM32_PLLI2SSRC_PLLSRC
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#define STM32_CK48MSEL STM32_CK48MSEL_PLLSAI
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#elif HAL_EXPECTED_SYSCLOCK == 168000000
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// medium frequency variants of F4, such as F405, F427
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#if STM32_HSECLK == 0U
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@ -234,8 +248,12 @@
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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#define STM32_I2SSRC STM32_I2SSRC_CKIN
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#ifndef STM32_PLLI2SN_VALUE
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#define STM32_PLLI2SN_VALUE 192
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#endif
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#ifndef STM32_PLLI2SR_VALUE
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#define STM32_PLLI2SR_VALUE 5
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#endif
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE FALSE
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