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AP_HAL_ChibiOS: Allow custom STM32_PLL1_DIVQ_VALUE for H7
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@ -171,7 +171,9 @@
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#define STM32_PLL1_DIVN_VALUE 100
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#define STM32_PLL1_DIVN_VALUE 100
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#endif
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#endif
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#define STM32_PLL1_DIVP_VALUE 2
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#define STM32_PLL1_DIVP_VALUE 2
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#ifndef STM32_PLL1_DIVQ_VALUE
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#define STM32_PLL1_DIVQ_VALUE 10
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#define STM32_PLL1_DIVQ_VALUE 10
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#endif
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#define STM32_PLL1_DIVR_VALUE 2
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#define STM32_PLL1_DIVR_VALUE 2
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#define STM32_PLL2_DIVN_VALUE 45
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#define STM32_PLL2_DIVN_VALUE 45
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