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HAL_ChibiOS: support no-crystal F3 setups

This commit is contained in:
Andrew Tridgell 2020-07-01 10:00:54 +10:00
parent 5a18b16f69
commit cfbfb27004
1 changed files with 27 additions and 3 deletions
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30
libraries/AP_HAL_ChibiOS/hwdef/common/stm32f3_mcuconf.h
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@ -32,12 +32,30 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_LSE_ENABLED FALSE
#if STM32_HSECLK == 0U
// use HSI, disable HSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE 16
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_RTCSEL STM32_RTCSEL_LSI
// can't do more than 64MHz with HSI
#undef HAL_EXPECTED_SYSCLOCK
#define HAL_EXPECTED_SYSCLOCK 64000000
#elif STM32_HSECLK == 8000000U
#define STM32_HSI_ENABLED FALSE
#define STM32_LSI_ENABLED FALSE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#if STM32_HSECLK == 8000000U
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
@ -46,7 +64,11 @@
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_HPRE STM32_HPRE_DIV1
#elif STM32_HSECLK == 24000000U
#define STM32_HSI_ENABLED FALSE
#define STM32_LSI_ENABLED FALSE
#define STM32_HSE_ENABLED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
@ -60,7 +82,9 @@
#endif
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#ifndef STM32_RTCSEL
#define STM32_RTCSEL STM32_RTCSEL_HSEDIV
#endif
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0