mirror of https://github.com/ArduPilot/ardupilot
HAL_ChibiOS: added support for more flexible memory regions
this allows for an arbitrary number of memory regions, with each one flagged as DMA safe, fast or normal
This commit is contained in:
Andrew Tridgell
parent
664e92ed7e
commit
cda1959629
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@ -54,7 +54,7 @@ void* Util::malloc_type(size_t size, AP_HAL::Util::Memory_Type mem_type)
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if (mem_type == AP_HAL::Util::MEM_DMA_SAFE) {
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return malloc_dma(size);
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} else if (mem_type == AP_HAL::Util::MEM_FAST) {
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return try_alloc_from_ccm_ram(size);
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return malloc_fastmem(size);
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} else {
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return calloc(1, size);
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}
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@ -68,16 +68,6 @@ void Util::free_type(void *ptr, size_t size, AP_HAL::Util::Memory_Type mem_type)
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}
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void* Util::try_alloc_from_ccm_ram(size_t size)
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{
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void *ret = malloc_ccm(size);
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if (ret == nullptr) {
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//we failed to allocate from CCM so we are going to try common SRAM
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ret = calloc(1, size);
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}
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return ret;
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}
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#ifdef ENABLE_HEAP
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void *Util::allocate_heap_memory(size_t size)
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@ -75,8 +75,6 @@ private:
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static ToneAlarmPwmGroup _toneAlarm_pwm_group;
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#endif
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void* try_alloc_from_ccm_ram(size_t size);
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uint32_t available_memory_in_ccm_ram(void);
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#if HAL_HAVE_IMU_HEATER
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struct {
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@ -31,6 +31,20 @@
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#include <stdarg.h>
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#include "stm32_util.h"
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#define MEM_REGION_FLAG_DMA_OK 1
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#define MEM_REGION_FLAG_FAST 2
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static struct memory_region {
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void *address;
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uint32_t size;
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uint32_t flags;
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memory_heap_t heap;
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} memory_regions[] = { HAL_MEMORY_REGIONS };
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// the first memory region is already setup as the ChibiOS
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// default heap, so we will index from 1 in the allocators
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#define NUM_MEMORY_REGIONS (sizeof(memory_regions)/sizeof(memory_regions[0]))
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#if CH_CFG_USE_HEAP == TRUE
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#define MIN_ALIGNMENT 8
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@ -41,18 +55,6 @@
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#define DMA_ALIGNMENT 8
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#endif
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#ifdef HAL_NO_CCM
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#undef CCM_RAM_SIZE_KB
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#endif
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#if defined(CCM_RAM_SIZE_KB)
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static memory_heap_t ccm_heap;
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#endif
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#if defined(DTCM_RAM_SIZE_KB)
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static memory_heap_t dtcm_heap;
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#endif
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// size of memory reserved for dma-capable alloc
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#ifndef DMA_RESERVE_SIZE
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#define DMA_RESERVE_SIZE 4096
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@ -62,96 +64,102 @@ static memory_heap_t dtcm_heap;
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static memory_heap_t dma_reserve_heap;
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#endif
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static void *malloc_dtcm(size_t size);
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/*
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initialise memory handling
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*/
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void malloc_init(void)
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{
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#if defined(CCM_RAM_SIZE_KB)
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chHeapObjectInit(&ccm_heap, (void *)CCM_BASE_ADDRESS, CCM_RAM_SIZE_KB*1024);
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#endif
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#if defined(DTCM_RAM_SIZE_KB)
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chHeapObjectInit(&dtcm_heap, (void *)DTCM_BASE_ADDRESS, DTCM_RAM_SIZE_KB*1024);
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#endif
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for (uint8_t i=1; i<NUM_MEMORY_REGIONS; i++) {
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chHeapObjectInit(&memory_regions[i].heap, memory_regions[i].address, memory_regions[i].size);
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}
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#if DMA_RESERVE_SIZE != 0
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/*
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create a DMA reserve heap, to ensure we keep some memory for DMA
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safe memory allocations
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*/
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void *dma_reserve = malloc_dtcm(DMA_RESERVE_SIZE);
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if (!dma_reserve) {
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dma_reserve = chHeapAllocAligned(NULL, DMA_RESERVE_SIZE, MIN_ALIGNMENT);
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}
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void *dma_reserve = malloc_dma(DMA_RESERVE_SIZE);
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osalDbgAssert(dma_reserve != NULL, "DMA reserve");
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chHeapObjectInit(&dma_reserve_heap, dma_reserve, DMA_RESERVE_SIZE);
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#endif //#if DMA_RESERVE_SIZE != 0
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}
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void *malloc_ccm(size_t size)
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{
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void *p = NULL;
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#if defined(CCM_RAM_SIZE_KB)
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p = chHeapAllocAligned(&ccm_heap, size, CH_HEAP_ALIGNMENT);
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if (p != NULL) {
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memset(p, 0, size);
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}
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#else
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(void)size;
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#endif
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return p;
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}
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static void *malloc_dtcm(size_t size)
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{
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void *p = NULL;
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#if defined(DTCM_RAM_SIZE_KB)
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p = chHeapAllocAligned(&dtcm_heap, size, DMA_ALIGNMENT);
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#else
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(void)size;
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#endif
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if (p != NULL) {
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memset(p, 0, size);
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}
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return p;
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}
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void *malloc(size_t size)
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static void *malloc_flags(size_t size, uint32_t flags)
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{
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if (size == 0) {
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return NULL;
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}
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void *p = chHeapAllocAligned(NULL, size, MIN_ALIGNMENT);
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if (p) {
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memset(p, 0, size);
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return p;
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const uint8_t alignment = (flags&MEM_REGION_FLAG_DMA_OK?DMA_ALIGNMENT:MIN_ALIGNMENT);
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void *p = NULL;
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if (flags & MEM_REGION_FLAG_DMA_OK) {
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// allocate multiple of DMA alignment
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size = (size + (DMA_ALIGNMENT-1)) & ~(DMA_ALIGNMENT-1);
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}
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if (!p) {
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// fall back to CCM memory
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p = malloc_ccm(size);
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// if no flags are set or this is a DMA request and default heap
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// is DMA safe then start with default heap
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if (flags == 0 || (flags == MEM_REGION_FLAG_DMA_OK &&
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(memory_regions[0].flags & MEM_REGION_FLAG_DMA_OK))) {
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p = chHeapAllocAligned(NULL, size, alignment);
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if (p) {
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return p;
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goto found;
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}
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}
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if (!p) {
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// fall back to DTCM memory
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p = malloc_dtcm(size);
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// try with matching flags
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for (uint8_t i=1; i<NUM_MEMORY_REGIONS; i++) {
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if ((flags & MEM_REGION_FLAG_DMA_OK) &&
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!(memory_regions[i].flags & MEM_REGION_FLAG_DMA_OK)) {
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continue;
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}
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if ((flags & MEM_REGION_FLAG_FAST) &&
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!(memory_regions[i].flags & MEM_REGION_FLAG_FAST)) {
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continue;
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}
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p = chHeapAllocAligned(&memory_regions[i].heap, size, alignment);
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if (p) {
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return p;
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goto found;
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}
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}
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// if this is a not a DMA request then we can fall back to any heap
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if (!(flags & MEM_REGION_FLAG_DMA_OK)) {
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for (uint8_t i=1; i<NUM_MEMORY_REGIONS; i++) {
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p = chHeapAllocAligned(&memory_regions[i].heap, size, alignment);
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if (p) {
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goto found;
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}
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}
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// try default heap
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p = chHeapAllocAligned(NULL, size, alignment);
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if (p) {
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goto found;
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}
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}
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#if DMA_RESERVE_SIZE != 0
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// fall back to DMA reserve
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p = chHeapAllocAligned(&dma_reserve_heap, size, MIN_ALIGNMENT);
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p = chHeapAllocAligned(&dma_reserve_heap, size, alignment);
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if (p) {
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memset(p, 0, size);
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return p;
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}
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#endif
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// failed
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return NULL;
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found:
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memset(p, 0, size);
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return p;
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}
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/*
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allocate normal memory
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*/
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void *malloc(size_t size)
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{
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return malloc_flags(size, 0);
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}
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/*
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@ -159,27 +167,15 @@ void *malloc(size_t size)
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*/
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void *malloc_dma(size_t size)
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{
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#if defined(STM32H7)
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size = (size + (DMA_ALIGNMENT-1)) & ~(DMA_ALIGNMENT-1);
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#endif
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void *p;
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#if defined(DTCM_RAM_SIZE_KB)
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p = malloc_dtcm(size);
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#else
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// if we don't have DTCM memory then assume that main heap is DMA-safe
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p = chHeapAllocAligned(NULL, size, DMA_ALIGNMENT);
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#endif
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#if DMA_RESERVE_SIZE != 0
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if (p == NULL) {
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p = chHeapAllocAligned(&dma_reserve_heap, size, DMA_ALIGNMENT);
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}
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#endif
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return malloc_flags(size, MEM_REGION_FLAG_DMA_OK);
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}
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if (p) {
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memset(p, 0, size);
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}
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osalDbgAssert((((uint32_t)p) & (DMA_ALIGNMENT-1)) == 0, "DMA alignment");
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return p;
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/*
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allocate fast memory
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*/
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void *malloc_fastmem(size_t size)
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{
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return malloc_flags(size, MEM_REGION_FLAG_FAST);
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}
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void *calloc(size_t nmemb, size_t size)
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@ -200,31 +196,39 @@ void free(void *ptr)
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size_t mem_available(void)
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{
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size_t totalp = 0;
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// get memory available on main heap
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chHeapStatus(NULL, &totalp, NULL);
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// we also need to add in memory that is not yet allocated to the heap
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totalp += chCoreGetStatusX();
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#if defined(CCM_RAM_SIZE_KB)
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size_t ccm_available = 0;
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chHeapStatus(&ccm_heap, &ccm_available, NULL);
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totalp += ccm_available;
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#endif
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#if defined(DTCM_RAM_SIZE_KB)
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size_t dtcm_available = 0;
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chHeapStatus(&dtcm_heap, &dtcm_available, NULL);
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totalp += dtcm_available;
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#endif
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// now our own heaps
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for (uint8_t i=1; i<NUM_MEMORY_REGIONS; i++) {
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size_t available = 0;
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chHeapStatus(&memory_regions[i].heap, &available, NULL);
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totalp += available;
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}
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#if DMA_RESERVE_SIZE != 0
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size_t reserve_available = 0;
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chHeapStatus(&dma_reserve_heap, &reserve_available, NULL);
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totalp += reserve_available;
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// and reserve DMA heap
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size_t available = 0;
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chHeapStatus(&dma_reserve_heap, &available, NULL);
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totalp += available;
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#endif
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return totalp;
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}
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#endif // CH_CFG_USE_HEAP
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/*
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flush all memory. Used in chSysHalt()
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*/
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void memory_flush_all(void)
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{
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for (uint8_t i=0; i<NUM_MEMORY_REGIONS; i++) {
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cacheBufferFlush(memory_regions[i].address, memory_regions[i].size);
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}
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}
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@ -95,14 +95,6 @@ void show_stack_usage(void)
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}
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#endif
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/*
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flush all memory. Used in chSysHalt()
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*/
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void memory_flush_all(void)
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{
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cacheBufferFlush(HAL_RAM_BASE_ADDRESS, HAL_RAM_SIZE_KB * 1024U);
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}
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/*
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set the utc time
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*/
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@ -30,8 +30,8 @@ void show_stack_usage(void);
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// allocation functions in malloc.c
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size_t mem_available(void);
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void *malloc_ccm(size_t size);
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void *malloc_dma(size_t size);
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void *malloc_fastmem(size_t size);
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// flush all dcache
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void memory_flush_all(void);
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@ -25,12 +25,12 @@ mcu = {
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# location of MCU serial number
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'UDID_START' : 0x1FFFF7E8,
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# base address of main memory
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'RAM_BASE_ADDRESS' : 0x20000000,
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# size of main memory
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'RAM_SIZE_KB' : 8,
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# ram map, as list of (address, size-kb, flags)
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# flags of 1 means DMA-capable
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# flags of 2 means faster memory for CPU intensive work
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'RAM_MAP' : [
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(0x20000000, 8, 1), # main memory, DMA safe
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]
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}
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ADC1_map = {
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@ -15,15 +15,13 @@ mcu = {
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# location of MCU serial number
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'UDID_START' : 0x1FFF7A10,
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# base address of main memory
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'RAM_BASE_ADDRESS' : 0x20000000,
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# size of main memory
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'RAM_SIZE_KB' : 128,
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# CCM ram address and size
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'CCM_BASE_ADDRESS' : 0x10000000,
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'CCM_RAM_SIZE_KB' : 64,
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# ram map, as list of (address, size-kb, flags)
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# flags of 1 means DMA-capable
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# flags of 2 means faster memory for CPU intensive work
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'RAM_MAP' : [
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(0x20000000, 128, 1), # main memory, DMA safe
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(0x10000000, 64, 2), # CCM memory, faster, but not DMA safe
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]
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}
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AltFunction_map = {
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@ -15,15 +15,13 @@ mcu = {
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# location of MCU serial number
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'UDID_START' : 0x1FFF7A10,
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# base address of main memory
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'RAM_BASE_ADDRESS' : 0x20000000,
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# size of main memory
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'RAM_SIZE_KB' : 128,
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# CCM ram address and size
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'CCM_BASE_ADDRESS' : 0x10000000,
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'CCM_RAM_SIZE_KB' : 64,
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# ram map, as list of (address, size-kb, flags)
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# flags of 1 means DMA-capable
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# flags of 2 means faster memory for CPU intensive work
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'RAM_MAP' : [
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(0x20000000, 128, 1), # main memory, DMA safe
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(0x10000000, 64, 2), # CCM memory, faster, but not DMA safe
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]
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}
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DMA_Map = {
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@ -15,11 +15,12 @@ mcu = {
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# location of MCU serial number
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'UDID_START' : 0x1FFF7A10,
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# base address of main memory
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'RAM_BASE_ADDRESS' : 0x20000000,
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# size of main memory
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'RAM_SIZE_KB' : 256
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# ram map, as list of (address, size-kb, flags)
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# flags of 1 means DMA-capable
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# flags of 2 means faster memory for CPU intensive work
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'RAM_MAP' : [
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(0x20000000, 256, 1), # main memory, DMA safe
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]
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}
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DMA_Map = {
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@ -15,15 +15,13 @@ mcu = {
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# location of MCU serial number
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'UDID_START' : 0x1FFF7A10,
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# base address of main memory
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'RAM_BASE_ADDRESS' : 0x20000000,
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# size of main memory
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'RAM_SIZE_KB' : 192,
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# CCM ram address and size
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'CCM_BASE_ADDRESS' : 0x10000000,
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'CCM_RAM_SIZE_KB' : 64,
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# ram map, as list of (address, size-kb, flags)
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# flags of 1 means DMA-capable
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# flags of 2 means faster memory for CPU intensive work
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'RAM_MAP' : [
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(0x20000000, 192, 1), # main memory, DMA safe
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(0x10000000, 64, 2), # CCM memory, faster, but not DMA safe
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]
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}
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DMA_Map = {
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@ -28,15 +28,13 @@ mcu = {
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# location of MCU serial number
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'UDID_START' : 0x1FFF7A10,
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# base address of main memory
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'RAM_BASE_ADDRESS' : 0x20000000,
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# size of main memory
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'RAM_SIZE_KB' : 320,
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# CCM ram address and size
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'CCM_BASE_ADDRESS' : 0x10000000,
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'CCM_RAM_SIZE_KB' : 64,
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# ram map, as list of (address, size-kb, flags)
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# flags of 1 means DMA-capable
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# flags of 2 means faster memory for CPU intensive work
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'RAM_MAP' : [
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(0x20000000, 320, 1), # main memory, DMA safe
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(0x10000000, 64, 1), # CCM memory, faster, not DMA safe
|
||||
]
|
||||
}
|
||||
|
||||
DMA_Map = {
|
||||
|
|
|
|||
|
|
@ -15,17 +15,13 @@ mcu = {
|
|||
# location of MCU serial number
|
||||
'UDID_START' : 0x1FF0F420,
|
||||
|
||||
# base address of main memory. We use SRAM1/SRAM2 as main memory
|
||||
# for maximum speed (using the dcache). DMA will be done from DTCM
|
||||
# memory
|
||||
'RAM_BASE_ADDRESS' : 0x20010000,
|
||||
|
||||
# size of main memory
|
||||
'RAM_SIZE_KB' : 256,
|
||||
|
||||
# DTCM ram address and size
|
||||
'DTCM_BASE_ADDRESS' : 0x20000000,
|
||||
'DTCM_RAM_SIZE_KB' : 64,
|
||||
# ram map, as list of (address, size-kb, flags)
|
||||
# flags of 1 means DMA-capable
|
||||
# flags of 2 means faster memory for CPU intensive work
|
||||
'RAM_MAP' : [
|
||||
(0x20010000, 256, 0), # main memory, not DMA safe
|
||||
(0x20000000, 64, 1), # DTCM memory, DMA safe
|
||||
]
|
||||
}
|
||||
|
||||
DMA_Map = {
|
||||
|
|
|
|||
|
|
@ -30,17 +30,13 @@ mcu = {
|
|||
# location of MCU serial number
|
||||
'UDID_START' : 0x1FF0F420,
|
||||
|
||||
# base address of main memory. We use SRAM1/SRAM2 as main memory
|
||||
# for maximum speed (using the dcache). DMA will be done from DTCM
|
||||
# memory
|
||||
'RAM_BASE_ADDRESS' : 0x20020000,
|
||||
|
||||
# size of main memory
|
||||
'RAM_SIZE_KB' : 384,
|
||||
|
||||
# DTCM ram address and size
|
||||
'DTCM_BASE_ADDRESS' : 0x20000000,
|
||||
'DTCM_RAM_SIZE_KB' : 128,
|
||||
# ram map, as list of (address, size-kb, flags)
|
||||
# flags of 1 means DMA-capable
|
||||
# flags of 2 means faster memory for CPU intensive work
|
||||
'RAM_MAP' : [
|
||||
(0x20020000, 384, 0), # SRAM1/SRAM2
|
||||
(0x20000000, 128, 1), # DTCM, DMA
|
||||
]
|
||||
}
|
||||
|
||||
DMA_Map = {
|
||||
|
|
|
|||
|
|
@ -29,17 +29,13 @@ mcu = {
|
|||
# location of MCU serial number
|
||||
'UDID_START' : 0x1FF0F420,
|
||||
|
||||
# base address of main memory. We use SRAM1/SRAM2 as main memory
|
||||
# for maximum speed (using the dcache). DMA will be done from DTCM
|
||||
# memory
|
||||
'RAM_BASE_ADDRESS' : 0x20020000,
|
||||
|
||||
# size of main memory
|
||||
'RAM_SIZE_KB' : 384,
|
||||
|
||||
# DTCM ram address and size
|
||||
'DTCM_BASE_ADDRESS' : 0x20000000,
|
||||
'DTCM_RAM_SIZE_KB' : 128,
|
||||
# ram map, as list of (address, size-kb, flags)
|
||||
# flags of 1 means DMA-capable
|
||||
# flags of 2 means faster memory for CPU intensive work
|
||||
'RAM_MAP' : [
|
||||
(0x20020000, 384, 0), # SRAM1/SRAM2
|
||||
(0x20000000, 128, 1), # DTCM, DMA
|
||||
]
|
||||
}
|
||||
|
||||
DMA_Map = {
|
||||
|
|
|
|||
|
|
@ -14,17 +14,16 @@ mcu = {
|
|||
# location of MCU serial number
|
||||
'UDID_START' : 0x1FF1E800,
|
||||
|
||||
# base address of main memory. We use AXI SRAM as main memory
|
||||
# for maximum speed (using the dcache). DMA will be done from DTCM
|
||||
# memory. Other SRAM areas will be added later
|
||||
'RAM_BASE_ADDRESS' : 0x24000000,
|
||||
|
||||
# size of main memory
|
||||
'RAM_SIZE_KB' : 512,
|
||||
|
||||
# DTCM ram address and size
|
||||
# 'DTCM_BASE_ADDRESS' : 0x20000000,
|
||||
# 'DTCM_RAM_SIZE_KB' : 128,
|
||||
# ram map, as list of (address, size-kb, flags)
|
||||
# flags of 1 means DMA-capable
|
||||
# flags of 2 means faster memory for CPU intensive work
|
||||
'RAM_MAP' : [
|
||||
(0x24000000, 512, 1), # AXI SRAM
|
||||
(0x30000000, 288, 1), # SRAM1, SRAM2, SRAM3
|
||||
(0x38000000, 64, 1), # SRAM4
|
||||
(0x00004000, 63, 2), # ITCM (first 1k removed, to keep address 0 unused)
|
||||
(0x20000000, 128, 2), # DTCM, tightly coupled, no DMA
|
||||
]
|
||||
}
|
||||
|
||||
pincount = {
|
||||
|
|
|
|||
|
|
@ -549,31 +549,18 @@ def write_mcu_config(f):
|
|||
f.write('#define BOARD_FLASH_SIZE %u\n' % flash_size)
|
||||
f.write('#define CRT1_AREAS_NUMBER 1\n')
|
||||
|
||||
# get core-coupled-memory if available (not be DMA capable)
|
||||
ccm_size = get_mcu_config('CCM_RAM_SIZE_KB')
|
||||
if ccm_size is not None:
|
||||
f.write('\n// core-coupled memory\n')
|
||||
f.write('#define CCM_RAM_SIZE_KB %u\n' % ccm_size)
|
||||
f.write('#define CCM_BASE_ADDRESS 0x%08x\n' % get_mcu_config('CCM_BASE_ADDRESS', True))
|
||||
|
||||
# get DTCM memory if available (DMA-capable with no cache flush/invalidate)
|
||||
dtcm_size = get_mcu_config('DTCM_RAM_SIZE_KB')
|
||||
if dtcm_size is not None:
|
||||
f.write('\n// DTCM memory\n')
|
||||
f.write('#define DTCM_RAM_SIZE_KB %u\n' % dtcm_size)
|
||||
f.write('#define DTCM_BASE_ADDRESS 0x%08x\n' % get_mcu_config('DTCM_BASE_ADDRESS', True))
|
||||
|
||||
flash_reserve_start = get_config(
|
||||
'FLASH_RESERVE_START_KB', default=16, type=int)
|
||||
f.write('\n// location of loaded firmware\n')
|
||||
f.write('#define FLASH_LOAD_ADDRESS 0x%08x\n' % (0x08000000 + flash_reserve_start*1024))
|
||||
f.write('\n')
|
||||
|
||||
ram_size_kb = get_mcu_config('RAM_SIZE_KB', True)
|
||||
ram_base_address = get_mcu_config('RAM_BASE_ADDRESS', True)
|
||||
f.write('// main memory size and address\n')
|
||||
f.write('#define HAL_RAM_SIZE_KB %uU\n' % ram_size_kb)
|
||||
f.write('#define HAL_RAM_BASE_ADDRESS 0x%08x\n' % ram_base_address)
|
||||
ram_map = get_mcu_config('RAM_MAP', True)
|
||||
f.write('// memory regions\n')
|
||||
regions = []
|
||||
for (address, size, flags) in ram_map:
|
||||
regions.append('{(void*)0x%08x, 0x%08x, 0x%02x, {}}' % (address, size*1024, flags))
|
||||
f.write('#define HAL_MEMORY_REGIONS %s\n' % ', '.join(regions))
|
||||
|
||||
f.write('\n// CPU serial number (12 bytes)\n')
|
||||
f.write('#define UDID_START 0x%08x\n\n' % get_mcu_config('UDID_START', True))
|
||||
|
|
@ -646,9 +633,8 @@ def write_ldscript(fname):
|
|||
# space to reserve for storage at end of flash
|
||||
flash_reserve_end = get_config('FLASH_RESERVE_END_KB', default=0, type=int)
|
||||
|
||||
# ram size
|
||||
ram_size = get_mcu_config('RAM_SIZE_KB', True)
|
||||
ram_base = get_mcu_config('RAM_BASE_ADDRESS', True)
|
||||
# ram layout
|
||||
ram_map = get_mcu_config('RAM_MAP', True)
|
||||
|
||||
flash_base = 0x08000000 + flash_reserve_start * 1024
|
||||
flash_length = flash_size - (flash_reserve_start + flash_reserve_end)
|
||||
|
|
@ -663,7 +649,7 @@ MEMORY
|
|||
}
|
||||
|
||||
INCLUDE common.ld
|
||||
''' % (flash_base, flash_length, ram_base, ram_size))
|
||||
''' % (flash_base, flash_length, ram_map[0][0], ram_map[0][1]))
|
||||
|
||||
def copy_common_linkerscript(outdir, hwdef):
|
||||
dirpath = os.path.dirname(hwdef)
|
||||
|
|
|
|||
Loading…
Reference in New Issue