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HAL_ChibiOS: fixed F745 database for new DMA system

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This commit is contained in:
Andrew Tridgell 2018-04-12 10:38:06 +10:00
parent eccc4f375b
commit c6d7691667
1 changed files with 92 additions and 91 deletions
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183
libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32F745xx.py
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@ -11,97 +11,98 @@ build = {
}
DMA_Map = {
# format is [DMA_TABLE, StreamNum]
# extracted from tabula-STM32F745-222.csvn
"ADC1" : [(2,0),(2,4)],
"ADC2" : [(2,2),(2,3)],
"ADC3" : [(2,0),(2,1)],
"CRYP_IN" : [(2,6)],
"CRYP_OUT" : [(2,5)],
"DAC1" : [(1,5)],
"DAC2" : [(1,6)],
"DCMI" : [(2,1),(2,7)],
"HASH_IN" : [(2,7)],
"I2C1_RX" : [(1,0),(1,5)],
"I2C1_TX" : [(1,6),(1,7)],
"I2C2_RX" : [(1,2),(1,3)],
"I2C2_TX" : [(1,7)],
"I2C3_RX" : [(1,1),(1,2)],
"I2C3_TX" : [(1,4)],
"I2C4_RX" : [(1,2),(1,5)],
"QUADSPI" : [(2,7)],
"SAI1_A" : [(2,1),(2,3)],
"SAI1_B" : [(2,5),(2,4)],
"SAI2_A" : [(2,4)],
"SAI2_B" : [(2,7),(2,6)],
"SDMMC1" : [(2,3),(2,6)],
"SPDIFRX_CS" : [(1,6)],
"SPDIFRX_DT" : [(1,1)],
"SPI1_RX" : [(2,0),(2,2)],
"SPI1_TX" : [(2,3),(2,5)],
"SPI2_RX" : [(1,3)],
"SPI2_TX" : [(1,4)],
"SPI3_RX" : [(1,0),(1,2)],
"SPI3_TX" : [(1,5),(1,7)],
"SPI4_RX" : [(2,0),(2,3)],
"SPI4_TX" : [(2,1),(2,4)],
"SPI5_RX" : [(2,3),(2,5)],
"SPI5_TX" : [(2,4),(2,6)],
"SPI6_RX" : [(2,6)],
"SPI6_TX" : [(2,5)],
"TIM1_CH1" : [(2,6),(2,1),(2,3)],
"TIM1_CH2" : [(2,6),(2,2)],
"TIM1_CH3" : [(2,6),(2,6)],
"TIM1_CH4" : [(2,4)],
"TIM1_COM" : [(2,4)],
"TIM1_TRIG" : [(2,0),(2,4)],
"TIM1_UP" : [(2,5)],
"TIM2_CH1" : [(1,5)],
"TIM2_CH2" : [(1,6)],
"TIM2_CH3" : [(1,1)],
"TIM2_CH4" : [(1,6),(1,7)],
"TIM2_UP" : [(1,1),(1,7)],
"TIM3_CH1" : [(1,4)],
"TIM3_CH2" : [(1,5)],
"TIM3_CH3" : [(1,7)],
"TIM3_CH4" : [(1,2)],
"TIM3_TRIG" : [(1,4)],
"TIM3_UP" : [(1,2)],
"TIM4_CH1" : [(1,0)],
"TIM4_CH2" : [(1,3)],
"TIM4_CH3" : [(1,7)],
"TIM4_UP" : [(1,6)],
"TIM5_CH1" : [(1,2)],
"TIM5_CH2" : [(1,4)],
"TIM5_CH3" : [(1,0)],
"TIM5_CH4" : [(1,1),(1,3)],
"TIM5_TRIG" : [(1,1),(1,3)],
"TIM5_UP" : [(1,0),(1,6)],
"TIM6_UP" : [(1,1)],
"TIM7_UP" : [(1,2),(1,4)],
"TIM8_CH1" : [(2,2),(2,2)],
"TIM8_CH2" : [(2,2),(2,3)],
"TIM8_CH3" : [(2,2),(2,4)],
"TIM8_CH4" : [(2,7)],
"TIM8_COM" : [(2,7)],
"TIM8_TRIG" : [(2,7)],
"TIM8_UP" : [(2,1)],
"UART4_RX" : [(1,2)],
"UART4_TX" : [(1,4)],
"UART5_RX" : [(1,0)],
"UART5_TX" : [(1,7)],
"UART7_RX" : [(1,3)],
"UART7_TX" : [(1,1)],
"UART8_RX" : [(1,6)],
"UART8_TX" : [(1,0)],
"USART1_RX" : [(2,2),(2,5)],
"USART1_TX" : [(2,7)],
"USART2_RX" : [(1,5)],
"USART2_TX" : [(1,6)],
"USART3_RX" : [(1,1)],
"USART3_TX" : [(1,3),(1,4)],
"USART6_RX" : [(2,1),(2,2)],
"USART6_TX" : [(2,6),(2,7)],
# format is (DMA_TABLE, StreamNum, Channel)
# extracted from tabula-STM32F745-222.csv
"ADC1" : [(2,0,0),(2,4,0)],
"ADC2" : [(2,2,1),(2,3,1)],
"ADC3" : [(2,0,2),(2,1,2)],
"CRYP_IN" : [(2,6,2)],
"CRYP_OUT" : [(2,5,2)],
"DAC1" : [(1,5,7)],
"DAC2" : [(1,6,7)],
"DCMI" : [(2,1,1),(2,7,1)],
"HASH_IN" : [(2,7,2)],
"I2C1_RX" : [(1,0,1),(1,5,1)],
"I2C1_TX" : [(1,6,1),(1,7,1)],
"I2C2_RX" : [(1,2,7),(1,3,7)],
"I2C2_TX" : [(1,7,7)],
"I2C3_RX" : [(1,1,1),(1,2,3)],
"I2C3_TX" : [(1,4,3)],
"I2C4" : [(1,2,2),(1,5,2)],
"QUADSPI" : [(2,7,3)],
"SAI1_A" : [(2,1,0),(2,3,0)],
"SAI1_B" : [(2,5,0),(2,4,1)],
"SAI2_A" : [(2,4,3)],
"SAI2_B" : [(2,7,0),(2,6,3)],
"SDMMC1" : [(2,3,4),(2,6,4)],
"SPDIFRX_CS" : [(1,6,0)],
"SPDIFRX_DT" : [(1,1,0)],
"SPI1_RX" : [(2,0,3),(2,2,3)],
"SPI1_TX" : [(2,3,3),(2,5,3)],
"SPI2_RX" : [(1,3,0)],
"SPI2_TX" : [(1,4,0)],
"SPI3_RX" : [(1,0,0),(1,2,0)],
"SPI3_TX" : [(1,5,0),(1,7,0)],
"SPI4_RX" : [(2,0,4),(2,3,5)],
"SPI4_TX" : [(2,1,4),(2,4,5)],
"SPI5_RX" : [(2,3,2),(2,5,7)],
"SPI5_TX" : [(2,4,2),(2,6,7)],
"SPI6_RX" : [(2,6,1)],
"SPI6_TX" : [(2,5,1)],
"TIM1_CH1" : [(2,6,0),(2,1,6),(2,3,6)],
"TIM1_CH2" : [(2,6,0),(2,2,6)],
"TIM1_CH3" : [(2,6,0),(2,6,6)],
"TIM1_CH4" : [(2,4,6)],
"TIM1_COM" : [(2,4,6)],
"TIM1_TRIG" : [(2,0,6),(2,4,6)],
"TIM1_UP" : [(2,5,6)],
"TIM2_CH1" : [(1,5,3)],
"TIM2_CH2" : [(1,6,3)],
"TIM2_CH3" : [(1,1,3)],
"TIM2_CH4" : [(1,6,3),(1,7,3)],
"TIM2_UP" : [(1,1,3),(1,7,3)],
"TIM3_CH1" : [(1,4,5)],
"TIM3_CH2" : [(1,5,5)],
"TIM3_CH3" : [(1,7,5)],
"TIM3_CH4" : [(1,2,5)],
"TIM3_TRIG" : [(1,4,5)],
"TIM3_UP" : [(1,2,5)],
"TIM4_CH1" : [(1,0,2)],
"TIM4_CH2" : [(1,3,2)],
"TIM4_CH3" : [(1,7,2)],
"TIM4_UP" : [(1,6,2)],
"TIM5_CH1" : [(1,2,6)],
"TIM5_CH2" : [(1,4,6)],
"TIM5_CH3" : [(1,0,6)],
"TIM5_CH4" : [(1,1,6),(1,3,6)],
"TIM5_TRIG" : [(1,1,6),(1,3,6)],
"TIM5_UP" : [(1,0,6),(1,6,6)],
"TIM6_UP" : [(1,1,7)],
"TIM7_UP" : [(1,2,1),(1,4,1)],
"TIM8_CH1" : [(2,2,0),(2,2,7)],
"TIM8_CH2" : [(2,2,0),(2,3,7)],
"TIM8_CH3" : [(2,2,0),(2,4,7)],
"TIM8_CH4" : [(2,7,7)],
"TIM8_COM" : [(2,7,7)],
"TIM8_TRIG" : [(2,7,7)],
"TIM8_UP" : [(2,1,7)],
"UART4_RX" : [(1,2,4)],
"UART4_TX" : [(1,4,4)],
"UART5_RX" : [(1,0,4)],
"UART5_TX" : [(1,7,4)],
"UART7_RX" : [(1,3,5)],
"UART7_TX" : [(1,1,5)],
"UART8_RX" : [(1,6,5)],
"UART8_TX" : [(1,0,5)],
"USART1_RX" : [(2,2,4),(2,5,4)],
"USART1_TX" : [(2,7,4)],
"USART2_RX" : [(1,5,4)],
"USART2_TX" : [(1,6,4)],
"USART3_RX" : [(1,1,4)],
"USART3_TX" : [(1,3,4),(1,4,7)],
"USART6_RX" : [(2,1,5),(2,2,5)],
"USART6_TX" : [(2,6,5),(2,7,5)],
"_RX" : [(1,2,2),(1,5,2)],
}
AltFunction_map = {