From c6c197d4fbc3cc11557207c33559103459ec2148 Mon Sep 17 00:00:00 2001
From: Andrew Tridgell <andrew@tridgell.net>
Date: Thu, 6 May 2021 09:50:46 +1000
Subject: [PATCH] HAL_ChibiOS: use SRAM1 as first ram segment on H7

this is needed to give the linker more than 128k for static variables
with double precision maths.
---
 libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py b/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py
index 7c479380be..5fe36da577 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py
+++ b/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py
@@ -26,8 +26,8 @@ mcu = {
     # flags of 2 means faster memory for CPU intensive work
     # flags of 4 means memory can be used for SDMMC DMA
     'RAM_MAP' : [
-        (0x20000000, 128, 2), # DTCM, tightly coupled, no DMA, fast
         (0x30000000, 256, 0), # SRAM1, SRAM2
+        (0x20000000, 128, 2), # DTCM, tightly coupled, no DMA, fast
         (0x24000000, 512, 4), # AXI SRAM. Use this for SDMMC IDMA ops
         (0x00000400,  63, 2), # ITCM (first 1k removed, to keep address 0 unused)
         (0x30040000,  32, 0), # SRAM3.