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https://github.com/ArduPilot/ardupilot
synced 2025-01-25 18:18:49 -04:00
HAL_ChibiOS: record reason for reset
allows us to tell if reset was due to watchdog
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@ -18,6 +18,7 @@
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#include "hal.h"
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#include "hal.h"
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#include "usbcfg.h"
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#include "usbcfg.h"
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#include "stm32_util.h"
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#include "stm32_util.h"
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#include "watchdog.h"
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/**
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/**
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@ -65,6 +66,7 @@ void __early_init(void) {
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void __late_init(void) {
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void __late_init(void) {
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halInit();
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halInit();
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chSysInit();
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chSysInit();
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stm32_watchdog_save_reason();
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#if CH_CFG_USE_HEAP == TRUE
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#if CH_CFG_USE_HEAP == TRUE
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malloc_init();
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malloc_init();
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#endif
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#endif
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@ -8,13 +8,38 @@
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#ifndef IWDG_BASE
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#ifndef IWDG_BASE
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#if defined(STM32H7)
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#if defined(STM32H7)
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#define IWDG_BASE 0x58004800
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#define IWDG_BASE 0x58004800
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#elif defined(STM32F7) || defined(STM32F4) || defined(STM32F1)
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#elif defined(STM32F7) || defined(STM32F4)
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#define IWDG_BASE 0x40003000
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#elif defined(STM32F1)
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#define IWDG_BASE 0x40003000
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#define IWDG_BASE 0x40003000
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#else
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#else
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#error "Unknown IWDG_BASE"
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#error "Unsupported IWDG MCU config"
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#endif
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#endif
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#endif
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#endif
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#ifndef RCC_BASE
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#error "Unsupported IWDG RCC MCU config"
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#endif
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/*
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defines for working out if the reset was from the watchdog
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*/
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#if defined(STM32H7)
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#define WDG_RESET_STATUS (*(__IO uint32_t *)(RCC_BASE + ))
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#define WDG_RESET_CLEAR (1U<<16)
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#define WDG_RESET_IS_IWDG (1U<<26)
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#elif defined(STM32F7) || defined(STM32F4)
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#define WDG_RESET_STATUS (*(__IO uint32_t *)(RCC_BASE + 0x74))
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#define WDG_RESET_CLEAR (1U<<24)
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#define WDG_RESET_IS_IWDG (1U<<29)
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#elif defined(STM32F1)
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#define WDG_RESET_STATUS (*(__IO uint32_t *)(RCC_BASE + 0x24))
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#define WDG_RESET_CLEAR (1U<<24)
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#define WDG_RESET_IS_IWDG (1U<<29)
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#else
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#error "Unsupported IWDG MCU config"
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#endif
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typedef struct
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typedef struct
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{
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{
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__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
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__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
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@ -46,3 +71,25 @@ void stm32_watchdog_pat(void)
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{
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{
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IWDGD.KR = 0xAAAA;
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IWDGD.KR = 0xAAAA;
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}
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}
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static bool was_watchdog_reset;
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/*
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save reason code for reset
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*/
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void stm32_watchdog_save_reason(void)
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{
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if (WDG_RESET_STATUS & WDG_RESET_IS_IWDG) {
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was_watchdog_reset = true;
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}
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WDG_RESET_STATUS = WDG_RESET_CLEAR;
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}
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/*
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return true if reboot was from a watchdog reset
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*/
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bool stm32_was_watchdog_reset(void)
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{
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return was_watchdog_reset;
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}
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@ -14,6 +14,16 @@ void stm32_watchdog_init(void);
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*/
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*/
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void stm32_watchdog_pat(void);
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void stm32_watchdog_pat(void);
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/*
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return true if reboot was from a watchdog reset
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*/
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bool stm32_was_watchdog_reset(void);
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/*
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save the reset reason code
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*/
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void stm32_watchdog_save_reason(void);
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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