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HAL_ChibiOS: support H7 with no crystal

This commit is contained in:
Andrew Tridgell 2020-07-01 10:35:00 +10:00
parent cfbfb27004
commit 84bd59a7bb
1 changed files with 56 additions and 12 deletions
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68
libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h
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@ -54,41 +54,54 @@
* Clock tree static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_HSI_ENABLED FALSE
#define STM32_LSI_ENABLED FALSE
#define STM32_CSI_ENABLED TRUE
#define STM32_CSI_ENABLED FALSE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_HSIDIV STM32_HSIDIV_DIV1
/*
* PLLs static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
#define STM32_PLLCFGR_MASK ~0
/*
setup PLLs based on HSE clock
*/
#if STM32_HSECLK == 8000000U
#if STM32_HSECLK == 0U
// no crystal, this gives 400MHz system clock
#define STM32_HSE_ENABLED FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_PLL1_DIVM_VALUE 4
#define STM32_PLL2_DIVM_VALUE 4
#define STM32_PLL3_DIVM_VALUE 4
#define STM32_PLLSRC STM32_PLLSRC_HSI_CK
#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
#define STM32_CKPERSEL STM32_CKPERSEL_HSI_CK
#elif STM32_HSECLK == 8000000U
// this gives 400MHz system clock
#define STM32_HSE_ENABLED TRUE
#define STM32_HSI_ENABLED FALSE
#define STM32_PLL1_DIVM_VALUE 1
#define STM32_PLL2_DIVM_VALUE 1
#define STM32_PLL3_DIVM_VALUE 2
#elif STM32_HSECLK == 16000000U
// this gives 400MHz system clock
#define STM32_HSE_ENABLED TRUE
#define STM32_HSI_ENABLED FALSE
#define STM32_PLL1_DIVM_VALUE 2
#define STM32_PLL2_DIVM_VALUE 2
#define STM32_PLL3_DIVM_VALUE 4
#elif STM32_HSECLK == 24000000U
// this gives 400MHz system clock
#define STM32_HSE_ENABLED TRUE
#define STM32_HSI_ENABLED FALSE
#define STM32_PLL1_DIVM_VALUE 3
#define STM32_PLL2_DIVM_VALUE 3
#define STM32_PLL3_DIVM_VALUE 6
#elif STM32_HSECLK == 25000000U
// this gives 400MHz system clock
#define STM32_HSE_ENABLED TRUE
#define STM32_HSI_ENABLED FALSE
#define STM32_PLL1_DIVM_VALUE 2
#define STM32_PLL2_DIVM_VALUE 2
#define STM32_PLL3_DIVM_VALUE 5
@ -96,7 +109,24 @@
#error "Unsupported HSE clock"
#endif
#if (STM32_HSECLK == 8000000U) || (STM32_HSECLK == 16000000U) || (STM32_HSECLK == 24000000U)
#if STM32_HSECLK == 0U
// no crystal
#define STM32_PLL1_DIVN_VALUE 50
#define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 8
#define STM32_PLL1_DIVR_VALUE 2
#define STM32_PLL2_DIVN_VALUE 16
#define STM32_PLL2_DIVP_VALUE 1
#define STM32_PLL2_DIVQ_VALUE 4
#define STM32_PLL2_DIVR_VALUE 2
#define STM32_PLL3_DIVN_VALUE 15
#define STM32_PLL3_DIVP_VALUE 3
#define STM32_PLL3_DIVQ_VALUE 5
#define STM32_PLL3_DIVR_VALUE 8
#elif (STM32_HSECLK == 8000000U) || (STM32_HSECLK == 16000000U) || (STM32_HSECLK == 24000000U)
// common clock tree for multiples of 8MHz crystals
#define STM32_PLL1_DIVN_VALUE 100
#define STM32_PLL1_DIVP_VALUE 2
@ -130,6 +160,16 @@
#define STM32_PLL3_DIVR_VALUE 8
#endif // clock selection
/*
* PLLs static settings.
* Reading STM32 Reference Manual is required.
*/
#ifndef STM32_PLLSRC
#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
#endif
#define STM32_PLLCFGR_MASK ~0
#define STM32_PLL1_ENABLED TRUE
#define STM32_PLL1_P_ENABLED TRUE
#define STM32_PLL1_Q_ENABLED TRUE
@ -165,7 +205,9 @@
* Peripherals clocks static settings.
* Reading STM32 Reference Manual is required.
*/
#ifndef STM32_MCO1SEL
#define STM32_MCO1SEL STM32_MCO1SEL_HSE_CK
#endif
#define STM32_MCO1PRE_VALUE 4
#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
#define STM32_MCO2PRE_VALUE 4
@ -174,7 +216,9 @@
#define STM32_STOPKERWUCK 0
#define STM32_STOPWUCK 0
#define STM32_RTCPRE_VALUE 8
#ifndef STM32_CKPERSEL
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
#endif
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
#define STM32_QSPISEL STM32_QSPISEL_HCLK
#define STM32_FMCSEL STM32_QSPISEL_HCLK