waf: build Richenpower on SITL by default

This commit is contained in:
Peter Barker 2022-07-13 21:18:04 +10:00 committed by Andrew Tridgell
parent 9acf4c88c8
commit 6c17fd7bac
1 changed files with 1 additions and 0 deletions

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@ -547,6 +547,7 @@ class sitl(Board):
cfg.define('AP_SIM_ENABLED', 1)
cfg.define('HAL_WITH_SPI', 1)
cfg.define('HAL_WITH_RAMTRON', 1)
cfg.define('AP_GENERATOR_RICHENPOWER_ENABLED', 1)
if self.with_can:
cfg.define('HAL_NUM_CAN_IFACES', 2)