From 5dd82f1d63311086d18601eb513f91b2c3bd436e Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Thu, 21 Feb 2019 22:04:18 +1100 Subject: [PATCH] HAL_ChibiOS: adjust 16MHz HSE settings for H743 (CubeH7) --- .../AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h b/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h index 6f21206f3a..3f84d6c185 100644 --- a/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h +++ b/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h @@ -112,20 +112,20 @@ #define STM32_PLL3_DIVR_VALUE 2 #elif STM32_HSECLK == 24000000U // this gives 384MHz system clock -#define STM32_PLL1_DIVM_VALUE 2 -#define STM32_PLL1_DIVN_VALUE 64 +#define STM32_PLL1_DIVM_VALUE 3 +#define STM32_PLL1_DIVN_VALUE 96 #define STM32_PLL1_DIVP_VALUE 2 #define STM32_PLL1_DIVQ_VALUE 16 #define STM32_PLL1_DIVR_VALUE 2 -#define STM32_PLL2_DIVM_VALUE 2 -#define STM32_PLL2_DIVN_VALUE 13 +#define STM32_PLL2_DIVM_VALUE 3 +#define STM32_PLL2_DIVN_VALUE 19 #define STM32_PLL2_DIVP_VALUE 1 #define STM32_PLL2_DIVQ_VALUE 2 #define STM32_PLL2_DIVR_VALUE 2 -#define STM32_PLL3_DIVM_VALUE 12 -#define STM32_PLL3_DIVN_VALUE 129 +#define STM32_PLL3_DIVM_VALUE 6 +#define STM32_PLL3_DIVN_VALUE 64 #define STM32_PLL3_DIVP_VALUE 2 #define STM32_PLL3_DIVQ_VALUE 2 #define STM32_PLL3_DIVR_VALUE 2