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HAL_ChibiOS: push H7 clock to 400MHz

This commit is contained in:
Andrew Tridgell 2019-03-04 19:36:51 +11:00
parent bef6a01682
commit 5bcfe41d1f
1 changed files with 6 additions and 6 deletions
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12
libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h
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@ -73,9 +73,9 @@
setup PLLs based on HSE clock setup PLLs based on HSE clock
*/ */
#if STM32_HSECLK == 8000000U #if STM32_HSECLK == 8000000U
// this gives 384MHz system clock // this gives 400MHz system clock
#define STM32_PLL1_DIVM_VALUE 1 #define STM32_PLL1_DIVM_VALUE 1
#define STM32_PLL1_DIVN_VALUE 96 #define STM32_PLL1_DIVN_VALUE 100
#define STM32_PLL1_DIVP_VALUE 2 #define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 16 #define STM32_PLL1_DIVQ_VALUE 16
#define STM32_PLL1_DIVR_VALUE 2 #define STM32_PLL1_DIVR_VALUE 2
@ -92,9 +92,9 @@
#define STM32_PLL3_DIVQ_VALUE 6 #define STM32_PLL3_DIVQ_VALUE 6
#define STM32_PLL3_DIVR_VALUE 3 #define STM32_PLL3_DIVR_VALUE 3
#elif STM32_HSECLK == 16000000U #elif STM32_HSECLK == 16000000U
// this gives 384MHz system clock // this gives 400MHz system clock
#define STM32_PLL1_DIVM_VALUE 2 #define STM32_PLL1_DIVM_VALUE 2
#define STM32_PLL1_DIVN_VALUE 96 #define STM32_PLL1_DIVN_VALUE 100
#define STM32_PLL1_DIVP_VALUE 2 #define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 16 #define STM32_PLL1_DIVQ_VALUE 16
#define STM32_PLL1_DIVR_VALUE 2 #define STM32_PLL1_DIVR_VALUE 2
@ -111,9 +111,9 @@
#define STM32_PLL3_DIVQ_VALUE 6 #define STM32_PLL3_DIVQ_VALUE 6
#define STM32_PLL3_DIVR_VALUE 3 #define STM32_PLL3_DIVR_VALUE 3
#elif STM32_HSECLK == 24000000U #elif STM32_HSECLK == 24000000U
// this gives 384MHz system clock // this gives 400MHz system clock
#define STM32_PLL1_DIVM_VALUE 3 #define STM32_PLL1_DIVM_VALUE 3
#define STM32_PLL1_DIVN_VALUE 96 #define STM32_PLL1_DIVN_VALUE 100
#define STM32_PLL1_DIVP_VALUE 2 #define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 16 #define STM32_PLL1_DIVQ_VALUE 16
#define STM32_PLL1_DIVR_VALUE 2 #define STM32_PLL1_DIVR_VALUE 2