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HAL_ChibiOS: fixed GPIOs for ESP8266 port

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This commit is contained in:
Andrew Tridgell 2018-02-04 15:35:24 +11:00
parent fa96e23552
commit 560948dc69
1 changed files with 11 additions and 6 deletions
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17
libraries/AP_HAL_ChibiOS/hwdef/fmuv4/hwdef.dat
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@ -48,7 +48,6 @@ PA5 SPI1_SCK SPI1
PA6 SPI1_MISO SPI1
PA7 SPI1_MOSI SPI1
PA8 8266_RTS INPUT
PA9 VBUS INPUT
PA10 FRSKY_INV OUTPUT
@ -63,12 +62,22 @@ PB0 TIM3_CH3 TIM3 PPMIN # RC Input PPM
PB1 LED_GREEN OUTPUT GPIO(0)
PB2 BOOT1 INPUT
PB3 LED_BLUE OUTPUT GPIO(1)
PB4 8266_GPIO2 OUTPUT GPIO(3)
PB5 VDD_BRICK_VALID INPUT
# USART1 is ESP8266
PB6 USART1_TX USART1
PB7 USART1_RX USART1
PA8 USART1_RTS USART1
# PE10 is not a hw CTS pin for USART1
PE10 8266_CTS INPUT
# make GPIOs for ESP8266 available via mavlink relay control as pins
# 60 to 63
PB4 8266_GPIO2 OUTPUT GPIO(60)
PE2 8266_GPI0 INPUT PULLUP GPIO(61)
PE5 8266_PD OUTPUT HIGH GPIO(62)
PE6 8266_RST OUTPUT HIGH GPIO(63)
PB8 I2C1_SCL I2C1
PB9 I2C1_SDA I2C1
@ -125,17 +134,13 @@ PD15 MPU9250_DRDY INPUT
# UART8 serial4 FrSky
PE0 UART8_RX UART8
PE1 UART8_TX UART8
PE2 8266_GPI0 OUTPUT GPIO(7)
PE3 VDD_SENSORS_EN OUTPUT HIGH
PE4 SPEKTRUM_PWR OUTPUT HIGH
PE5 8266_PD OUTPUT LOW
PE6 8266_RST OUTPUT LOW
# UART7 is debug
PE7 UART7_RX UART7
PE8 UART7_TX UART7
PE9 TIM1_CH1 TIM1 PWM(4) GPIO(53)
PE10 8266_CTS OUTPUT HIGH
PE11 TIM1_CH2 TIM1 PWM(3) GPIO(52)
PE12 MAG_DRDY INPUT
PE13 TIM1_CH3 TIM1 PWM(2) GPIO(51)