From 52b47e499b29bd13d1068e0e4947c2909be19e13 Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Fri, 8 Feb 2019 13:19:13 +1100 Subject: [PATCH] HAL_ChibiOS: fixed H7 clock tree for ADC driver --- .../hwdef/common/stm32h7_mcuconf.h | 49 +++++++------------ 1 file changed, 17 insertions(+), 32 deletions(-) diff --git a/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h b/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h index 128025902f..a1d0aed7a3 100644 --- a/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h +++ b/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h @@ -27,18 +27,6 @@ #define STM32_LSEDRV (3U << 3U) #endif -#ifndef STM32_PLL1_DIVM_VALUE -#define STM32_PLL1_DIVM_VALUE (STM32_HSECLK / 2000000U) -#endif - -#ifndef STM32_PLL2_DIVM_VALUE -#define STM32_PLL2_DIVM_VALUE (STM32_HSECLK / 2000000U) -#endif - -#ifndef STM32_PLL3_DIVM_VALUE -#define STM32_PLL3_DIVM_VALUE (STM32_HSECLK / 1000000U) -#endif - /* * General settings. */ @@ -66,8 +54,8 @@ * Clock tree static settings. * Reading STM32 Reference Manual is required. */ -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE +#define STM32_HSI_ENABLED FALSE +#define STM32_LSI_ENABLED FALSE #define STM32_CSI_ENABLED TRUE #define STM32_HSI48_ENABLED TRUE #define STM32_HSE_ENABLED TRUE @@ -80,41 +68,38 @@ */ #define STM32_PLLSRC STM32_PLLSRC_HSE_CK #define STM32_PLLCFGR_MASK ~0 + #define STM32_PLL1_ENABLED TRUE #define STM32_PLL1_P_ENABLED TRUE #define STM32_PLL1_Q_ENABLED TRUE #define STM32_PLL1_R_ENABLED TRUE -#ifndef STM32_PLL1_DIVM_VALUE -#define STM32_PLL1_DIVM_VALUE 4 -#endif -#define STM32_PLL1_DIVN_VALUE 400 +#define STM32_PLL1_DIVM_VALUE (STM32_HSECLK / 8000000U) +#define STM32_PLL1_DIVN_VALUE 24 #define STM32_PLL1_FRACN_VALUE 0 #define STM32_PLL1_DIVP_VALUE 2 #define STM32_PLL1_DIVQ_VALUE 4 #define STM32_PLL1_DIVR_VALUE 2 + #define STM32_PLL2_ENABLED TRUE #define STM32_PLL2_P_ENABLED TRUE #define STM32_PLL2_Q_ENABLED TRUE #define STM32_PLL2_R_ENABLED TRUE -#ifndef STM32_PLL2_DIVM_VALUE -#define STM32_PLL2_DIVM_VALUE 4 -#endif -#define STM32_PLL2_DIVN_VALUE 400 +#define STM32_PLL2_DIVM_VALUE (STM32_HSECLK / 8000000U) +#define STM32_PLL2_DIVN_VALUE 19 #define STM32_PLL2_FRACN_VALUE 0 -#define STM32_PLL2_DIVP_VALUE 40 -#define STM32_PLL2_DIVQ_VALUE 8 -#define STM32_PLL2_DIVR_VALUE 8 +#define STM32_PLL2_DIVP_VALUE 1 +#define STM32_PLL2_DIVQ_VALUE 2 +#define STM32_PLL2_DIVR_VALUE 2 + #define STM32_PLL3_ENABLED TRUE #define STM32_PLL3_P_ENABLED TRUE #define STM32_PLL3_Q_ENABLED TRUE #define STM32_PLL3_R_ENABLED TRUE -#ifndef STM32_PLL3_DIVM_VALUE -#define STM32_PLL3_DIVM_VALUE 8 -#endif -#define STM32_PLL3_DIVN_VALUE 336 +#define STM32_PLL3_DIVM_VALUE (STM32_HSECLK / 2000000U) +#define STM32_PLL3_DIVN_VALUE 129 #define STM32_PLL3_FRACN_VALUE 0 #define STM32_PLL3_DIVP_VALUE 2 -#define STM32_PLL3_DIVQ_VALUE 7 +#define STM32_PLL3_DIVQ_VALUE 2 #define STM32_PLL3_DIVR_VALUE 2 /* @@ -134,7 +119,7 @@ * Peripherals clocks static settings. * Reading STM32 Reference Manual is required. */ -#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK +#define STM32_MCO1SEL STM32_MCO1SEL_HSE_CK #define STM32_MCO1PRE_VALUE 4 #define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK #define STM32_MCO2PRE_VALUE 4 @@ -157,7 +142,7 @@ #define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 #define STM32_CECSEL STM32_CECSEL_LSE_CK -#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK +#define STM32_USBSEL STM32_USBSEL_PLL1_Q_CK #define STM32_I2C123SEL STM32_I2C123SEL_PCLK1 #define STM32_RNGSEL STM32_RNGSEL_HSI48_CK #define STM32_USART16SEL STM32_USART16SEL_PCLK2