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AP_HAL_ChibiOS: Support 32MHz HSE on H7 MCUs
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@ -152,6 +152,15 @@
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#define STM32_PLL1_DIVM_VALUE 2
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#define STM32_PLL2_DIVM_VALUE 5
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#define STM32_PLL3_DIVM_VALUE 5
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#elif STM32_HSECLK == 32000000U
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// this gives 400MHz system clock
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#define STM32_HSE_ENABLED TRUE
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#define STM32_HSI_ENABLED FALSE
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#define STM32_PLL1_DIVM_VALUE 4
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#define STM32_PLL2_DIVM_VALUE 4
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#define STM32_PLL3_DIVM_VALUE 8
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#else
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#error "Unsupported HSE clock"
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#endif
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@ -172,7 +181,7 @@
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#define STM32_PLL3_DIVQ_VALUE 5
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#define STM32_PLL3_DIVR_VALUE 8
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#elif (STM32_HSECLK == 8000000U) || (STM32_HSECLK == 16000000U)
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#elif (STM32_HSECLK == 8000000U) || (STM32_HSECLK == 16000000U) || (STM32_HSECLK == 32000000U)
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// common clock tree for multiples of 8MHz crystals
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#ifdef HAL_CUSTOM_MCU_CLOCKRATE
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#if HAL_CUSTOM_MCU_CLOCKRATE == 480000000
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