mirror of https://github.com/ArduPilot/ardupilot
HAL_ChibiOS: added missing DMA table for STM32F405
This commit is contained in:
Andrew Tridgell
parent
964f081bab
commit
4b5e617673
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@ -480,488 +480,6 @@ AltFunction_map = {
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"PH9:I2C3_SMBA" : 4,
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"PH9:TIM12_CH2" : 9,
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}
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AltFunction_map = {
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# format is PIN:FUNCTION : AFNUM
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# extracted from tabula-AF-F405.csv
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"PA0:ETH_MII_CRS" : 11,
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"PA0:EVENTOUT" : 15,
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"PA0:TIM2_CH1_ETR" : 1,
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"PA0:TIM5_CH1" : 2,
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"PA0:TIM8_ETR" : 3,
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"PA0:UART4_TX" : 8,
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"PA0:USART2_CTS" : 7,
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"PA10:DCMI_D1" : 13,
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"PA10:EVENTOUT" : 15,
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"PA10:OTG_FS_ID" : 10,
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"PA10:TIM1_CH3" : 1,
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"PA10:USART1_RX" : 7,
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"PA11:CAN1_RX" : 9,
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"PA11:EVENTOUT" : 15,
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"PA11:OTG_FS_DM" : 10,
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"PA11:TIM1_CH4" : 1,
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"PA11:USART1_CTS" : 7,
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"PA12:CAN1_TX" : 9,
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"PA12:EVENTOUT" : 15,
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"PA12:OTG_FS_DP" : 10,
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"PA12:TIM1_ETR" : 1,
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"PA12:USART1_RTS" : 7,
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"PA13:EVENTOUT" : 15,
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"PA13:JTMS-SWDIO" : 0,
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"PA14:EVENTOUT" : 15,
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"PA14:JTCK-SWCLK" : 0,
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"PA1:ETH_MII_RX_CLK" : 11,
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"PA1:ETH_RMII__REF_CLK" : 11,
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"PA1:EVENTOUT" : 15,
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"PA1:TIM2_CH2" : 1,
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"PA1:TIM5_CH2" : 2,
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"PA1:UART4_RX" : 8,
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"PA1:USART2_RTS" : 7,
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"PA2:ETH_MDIO" : 11,
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"PA2:EVENTOUT" : 15,
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"PA2:TIM2_CH3" : 1,
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"PA2:TIM5_CH3" : 2,
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"PA2:TIM9_CH1" : 3,
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"PA2:USART2_TX" : 7,
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"PA3:ETH_MII_COL" : 11,
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"PA3:EVENTOUT" : 15,
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"PA3:OTG_HS_ULPI_D0" : 10,
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"PA3:TIM2_CH4" : 1,
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"PA3:TIM5_CH4" : 2,
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"PA3:TIM9_CH2" : 3,
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"PA3:USART2_RX" : 7,
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"PA4:DCMI_HSYNC" : 13,
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"PA4:EVENTOUT" : 15,
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"PA4:OTG_HS_SOF" : 12,
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"PA4:SPI1_NSS" : 5,
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"PA4:SPI3_NSSI2S3_WS" : 6,
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"PA4:USART2_CK" : 7,
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"PA5:EVENTOUT" : 15,
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"PA5:OTG_HS_ULPI_CK" : 10,
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"PA5:SPI1_SCK" : 5,
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"PA5:TIM2_CH1_ETR" : 1,
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"PA5:TIM8_CH1N" : 3,
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"PA6:DCMI_PIXCK" : 13,
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"PA6:EVENTOUT" : 15,
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"PA6:SPI1_MISO" : 5,
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"PA6:TIM13_CH1" : 9,
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"PA6:TIM1_BKIN" : 1,
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"PA6:TIM3_CH1" : 2,
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"PA6:TIM8_BKIN" : 3,
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"PA7:ETH_MII_RX_DV" : 11,
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"PA7:ETH_RMII_CRS_DV" : 11,
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"PA7:EVENTOUT" : 15,
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"PA7:SPI1_MOSI" : 5,
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"PA7:TIM14_CH1" : 9,
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"PA7:TIM1_CH1N" : 1,
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"PA7:TIM3_CH2" : 2,
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"PA7:TIM8_CH1N" : 3,
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"PA8:EVENTOUT" : 15,
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"PA8:I2C3_SCL" : 4,
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"PA8:MCO1" : 0,
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"PA8:OTG_FS_SOF" : 10,
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"PA8:TIM1_CH1" : 1,
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"PA8:USART1_CK" : 7,
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"PA9:DCMI_D0" : 13,
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"PA9:EVENTOUT" : 15,
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"PA9:I2C3_SMBA" : 4,
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"PA9:TIM1_CH2" : 1,
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"PA9:USART1_TX" : 7,
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"PB0:ETH_MII_RXD2" : 11,
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"PB0:EVENTOUT" : 15,
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"PB0:OTG_HS_ULPI_D1" : 10,
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"PB0:TIM1_CH2N" : 1,
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"PB0:TIM3_CH3" : 2,
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"PB0:TIM8_CH2N" : 3,
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"PB10:ETH_MII_RX_ER" : 11,
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"PB10:EVENTOUT" : 15,
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"PB10:I2C2_SCL" : 4,
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"PB10:OTG_HS_ULPI_D3" : 10,
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"PB10:SPI2_SCKI2S2_CK" : 5,
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"PB10:TIM2_CH3" : 1,
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"PB10:USART3_TX" : 7,
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"PB11:ETH_MII_TX_EN" : 11,
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"PB11:ETH_RMII_TX_EN" : 11,
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"PB11:EVENTOUT" : 15,
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"PB11:I2C2_SDA" : 4,
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"PB11:OTG_HS_ULPI_D4" : 10,
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"PB11:TIM2_CH4" : 1,
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"PB11:USART3_RX" : 7,
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"PB12:CAN2_RX" : 9,
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"PB12:ETH_MII_TXD0" : 11,
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"PB12:ETH_RMII_TXD0" : 11,
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"PB12:EVENTOUT" : 15,
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"PB12:I2C2_SMBA" : 4,
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"PB12:OTG_HS_ID" : 12,
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"PB12:OTG_HS_ULPI_D5" : 10,
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"PB12:SPI2_NSSI2S2_WS" : 5,
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"PB12:TIM1_BKIN" : 1,
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"PB12:USART3_CK" : 7,
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"PB13:CAN2_TX" : 9,
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"PB13:ETH_MII_TXD1" : 11,
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"PB13:ETH_RMII_TXD1" : 11,
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"PB13:EVENTOUT" : 15,
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"PB13:OTG_HS_ULPI_D6" : 10,
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"PB13:SPI2_SCKI2S2_CK" : 5,
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"PB13:TIM1_CH1N" : 1,
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"PB13:USART3_CTS" : 7,
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"PB14:EVENTOUT" : 15,
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"PB14:I2S2EXT_SD" : 6,
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"PB14:OTG_HS_DM" : 12,
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"PB14:SPI2_MISO" : 5,
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"PB14:TIM12_CH1" : 9,
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"PB14:TIM1_CH2N" : 1,
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"PB14:TIM8_CH2N" : 3,
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"PB14:USART3_RTS" : 7,
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"PB1:ETH_MII_RXD3" : 11,
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"PB1:EVENTOUT" : 15,
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"PB1:OTG_HS_ULPI_D2" : 10,
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"PB1:TIM1_CH3N" : 1,
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"PB1:TIM3_CH4" : 2,
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"PB1:TIM8_CH3N" : 3,
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"PB2:EVENTOUT" : 15,
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"PB3:EVENTOUT" : 15,
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"PB3:JTDO" : 0,
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"PB3:SPI1_SCK" : 5,
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"PB3:SPI3_SCKI2S3_CK" : 6,
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"PB3:TIM2_CH2" : 1,
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"PB3:TRACESWO" : 0,
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"PB4:EVENTOUT" : 15,
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"PB4:I2S3EXT_SD" : 7,
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"PB4:NJTRST" : 0,
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"PB4:SPI1_MISO" : 5,
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"PB4:SPI3_MISO" : 6,
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"PB4:TIM3_CH1" : 2,
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"PB5:CAN2_RX" : 9,
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"PB5:DCMI_D10" : 13,
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"PB5:ETH_PPS_OUT" : 11,
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"PB5:EVENTOUT" : 15,
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"PB5:I2C1_SMBA" : 4,
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"PB5:OTG_HS_ULPI_D7" : 10,
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"PB5:SPI1_MOSI" : 5,
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"PB5:SPI3_MOSII2S3_SD" : 6,
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"PB5:TIM3_CH2" : 2,
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"PB6:CAN2_TX" : 9,
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"PB6:DCMI_D5" : 13,
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"PB6:EVENTOUT" : 15,
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"PB6:I2C1_SCL" : 4,
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"PB6:TIM4_CH1" : 2,
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"PB6:USART1_TX" : 7,
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"PB7:DCMI_VSYNC" : 13,
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"PB7:EVENTOUT" : 15,
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"PB7:FSMC_NL" : 12,
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"PB7:I2C1_SDA" : 4,
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"PB7:TIM4_CH2" : 2,
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"PB7:USART1_RX" : 7,
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"PB8:CAN1_RX" : 9,
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"PB8:DCMI_D6" : 13,
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"PB8:ETH_MII_TXD3" : 11,
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"PB8:EVENTOUT" : 15,
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"PB8:I2C1_SCL" : 4,
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"PB8:SDIO_D4" : 12,
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"PB8:TIM10_CH1" : 3,
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"PB8:TIM4_CH3" : 2,
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"PB9:CAN1_TX" : 9,
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"PB9:DCMI_D7" : 13,
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"PB9:EVENTOUT" : 15,
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"PB9:I2C1_SDA" : 4,
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"PB9:SDIO_D5" : 12,
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"PB9:SPI2_NSSI2S2_WS" : 5,
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"PB9:TIM11_CH1" : 3,
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"PB9:TIM4_CH4" : 2,
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"PC0:EVENTOUT" : 15,
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"PC0:OTG_HS_ULPI_STP" : 10,
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"PC10:DCMI_D8" : 13,
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"PC10:EVENTOUT" : 15,
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"PC10:I2S3_CK" : 6,
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"PC10:SDIO_D2" : 12,
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"PC10:SPI3_SCK" : 6,
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"PC10:UART4_TX" : 8,
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"PC10:USART3_TX" : 7,
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"PC11:DCMI_D4" : 13,
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"PC11:EVENTOUT" : 15,
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"PC11:I2S3EXT_SD" : 5,
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"PC11:SDIO_D3" : 12,
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"PC11:SPI3_MISO" : 6,
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"PC11:UART4_RX" : 8,
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"PC11:USART3_RX" : 7,
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"PC12:DCMI_D9" : 13,
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"PC12:EVENTOUT" : 15,
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"PC12:SDIO_CK" : 12,
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"PC12:SPI3_MOSII2S3_SD" : 6,
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"PC12:UART5_TX" : 8,
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"PC12:USART3_CK" : 7,
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"PC13:EVENTOUT" : 15,
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"PC14:EVENTOUT" : 15,
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"PC1:ETH_MDC" : 11,
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"PC1:EVENTOUT" : 15,
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"PC2:ETH_MII_TXD2" : 11,
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"PC2:EVENTOUT" : 15,
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"PC2:I2S2EXT_SD" : 6,
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"PC2:OTG_HS_ULPI_DIR" : 10,
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"PC2:SPI2_MISO" : 5,
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"PC3:ETH_MII_TX_CLK" : 11,
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"PC3:EVENTOUT" : 15,
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"PC3:OTG_HS_ULPI_NXT" : 10,
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"PC3:SPI2_MOSII2S2_SD" : 5,
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"PC4:ETH_MII_RXD0" : 11,
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"PC4:ETH_RMII_RXD0" : 11,
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"PC4:EVENTOUT" : 15,
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"PC5:ETH_MII_RXD1" : 11,
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"PC5:ETH_RMII_RXD1" : 11,
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"PC5:EVENTOUT" : 15,
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"PC6:DCMI_D0" : 13,
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"PC6:EVENTOUT" : 15,
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"PC6:I2S2_MCK" : 5,
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"PC6:SDIO_D6" : 12,
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"PC6:TIM3_CH1" : 2,
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"PC6:TIM8_CH1" : 3,
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"PC6:USART6_TX" : 8,
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"PC7:DCMI_D1" : 13,
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"PC7:EVENTOUT" : 15,
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"PC7:I2S3_MCK" : 6,
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"PC7:SDIO_D7" : 12,
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"PC7:TIM3_CH2" : 2,
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"PC7:TIM8_CH2" : 3,
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"PC7:USART6_RX" : 8,
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"PC8:DCMI_D2" : 13,
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"PC8:EVENTOUT" : 15,
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"PC8:SDIO_D0" : 12,
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"PC8:TIM3_CH3" : 2,
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"PC8:TIM8_CH3" : 3,
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"PC8:USART6_CK" : 8,
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"PC9:DCMI_D3" : 13,
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"PC9:EVENTOUT" : 15,
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"PC9:I2C3_SDA" : 4,
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"PC9:I2S_CKIN" : 5,
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"PC9:MCO2" : 0,
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"PC9:SDIO_D1" : 12,
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"PC9:TIM3_CH4" : 2,
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"PC9:TIM8_CH4" : 3,
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"PD10:EVENTOUT" : 15,
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"PD10:FSMC_D15" : 12,
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"PD10:USART3_CK" : 7,
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"PD11:EVENTOUT" : 15,
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"PD11:FSMC_A16" : 12,
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"PD11:USART3_CTS" : 7,
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"PD12:EVENTOUT" : 15,
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"PD12:FSMC_A17" : 12,
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"PD12:TIM4_CH1" : 2,
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"PD12:USART3_RTS" : 7,
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"PD13:EVENTOUT" : 15,
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"PD13:FSMC_A18" : 12,
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"PD13:TIM4_CH2" : 2,
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"PD14:EVENTOUT" : 15,
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"PD14:FSMC_D0" : 12,
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"PD14:TIM4_CH3" : 2,
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"PD15:EVENTOUT" : 15,
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"PD15:FSMC_D1" : 12,
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"PD15:TIM4_CH4" : 2,
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"PD1:CAN1_TX" : 9,
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"PD1:EVENTOUT" : 15,
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"PD1:FSMC_D3" : 12,
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"PD2:DCMI_D11" : 13,
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"PD2:EVENTOUT" : 15,
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"PD2:SDIO_CMD" : 12,
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"PD2:TIM3_ETR" : 2,
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"PD2:UART5_RX" : 8,
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"PD3:EVENTOUT" : 15,
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"PD3:FSMC_CLK" : 12,
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"PD3:USART2_CTS" : 7,
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"PD4:EVENTOUT" : 15,
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"PD4:FSMC_NOE" : 12,
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"PD4:USART2_RTS" : 7,
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"PD5:EVENTOUT" : 15,
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"PD5:FSMC_NWE" : 12,
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"PD5:USART2_TX" : 7,
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"PD6:EVENTOUT" : 15,
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"PD6:FSMC_NWAIT" : 12,
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"PD6:USART2_RX" : 7,
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"PD7:EVENTOUT" : 15,
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"PD7:FSMC_NCE2" : 12,
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"PD7:FSMC_NE1" : 12,
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"PD7:USART2_CK" : 7,
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"PD8:EVENTOUT" : 15,
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"PD8:FSMC_D13" : 12,
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"PD8:USART3_TX" : 7,
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"PD9:EVENTOUT" : 15,
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"PD9:FSMC_D14" : 12,
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"PD9:USART3_RX" : 7,
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"PE0:DCMI_D2" : 13,
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"PE0:EVENTOUT" : 15,
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"PE0:FSMC_NBL0" : 12,
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"PE0:TIM4_ETR" : 2,
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"PE10:EVENTOUT" : 15,
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"PE10:FSMC_D7" : 12,
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"PE10:TIM1_CH2N" : 1,
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"PE11:EVENTOUT" : 15,
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"PE11:FSMC_D8" : 12,
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"PE11:TIM1_CH2" : 1,
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"PE12:EVENTOUT" : 15,
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"PE12:FSMC_D9" : 12,
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"PE12:TIM1_CH3N" : 1,
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"PE13:EVENTOUT" : 15,
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"PE13:FSMC_D10" : 12,
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"PE13:TIM1_CH3" : 1,
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"PE14:EVENTOUT" : 15,
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"PE14:FSMC_D11" : 12,
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"PE14:TIM1_CH4" : 1,
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"PE1:DCMI_D3" : 13,
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"PE1:EVENTOUT" : 15,
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"PE1:FSMC_NBL1" : 12,
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"PE2:ETH_MII_TXD3" : 11,
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"PE2:EVENTOUT" : 15,
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"PE2:FSMC_A23" : 12,
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"PE2:TRACECLK" : 0,
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"PE3:EVENTOUT" : 15,
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"PE3:FSMC_A19" : 12,
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"PE3:TRACED0" : 0,
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"PE4:DCMI_D4" : 13,
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"PE4:EVENTOUT" : 15,
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"PE4:FSMC_A20" : 12,
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"PE4:TRACED1" : 0,
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"PE5:DCMI_D6" : 13,
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"PE5:EVENTOUT" : 15,
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"PE5:FSMC_A21" : 12,
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"PE5:TIM9_CH1" : 3,
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"PE5:TRACED2" : 0,
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"PE6:DCMI_D7" : 13,
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"PE6:EVENTOUT" : 15,
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"PE6:FSMC_A22" : 12,
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"PE6:TIM9_CH2" : 3,
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"PE6:TRACED3" : 0,
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"PE7:EVENTOUT" : 15,
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"PE7:FSMC_D4" : 12,
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"PE7:TIM1_ETR" : 1,
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"PE8:EVENTOUT" : 15,
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"PE8:FSMC_D5" : 12,
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"PE8:TIM1_CH1N" : 1,
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"PE9:EVENTOUT" : 15,
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"PE9:FSMC_D6" : 12,
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"PE9:TIM1_CH1" : 1,
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"PF0:EVENTOUT" : 15,
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"PF0:FSMC_A0" : 12,
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"PF0:I2C2_SDA" : 4,
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"PF10:EVENTOUT" : 15,
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"PF10:FSMC_INTR" : 12,
|
||||
"PF11:DCMI_D12" : 13,
|
||||
"PF11:EVENTOUT" : 15,
|
||||
"PF12:EVENTOUT" : 15,
|
||||
"PF12:FSMC_A6" : 12,
|
||||
"PF13:EVENTOUT" : 15,
|
||||
"PF13:FSMC_A7" : 12,
|
||||
"PF14:EVENTOUT" : 15,
|
||||
"PF14:FSMC_A8" : 12,
|
||||
"PF1:EVENTOUT" : 15,
|
||||
"PF1:FSMC_A1" : 12,
|
||||
"PF1:I2C2_SCL" : 4,
|
||||
"PF2:EVENTOUT" : 15,
|
||||
"PF2:FSMC_A2" : 12,
|
||||
"PF2:I2C2_SMBA" : 4,
|
||||
"PF3:EVENTOUT" : 15,
|
||||
"PF3:FSMC_A3" : 12,
|
||||
"PF4:EVENTOUT" : 15,
|
||||
"PF4:FSMC_A4" : 12,
|
||||
"PF5:EVENTOUT" : 15,
|
||||
"PF5:FSMC_A5" : 12,
|
||||
"PF6:EVENTOUT" : 15,
|
||||
"PF6:FSMC_NIORD" : 12,
|
||||
"PF6:TIM10_CH1" : 3,
|
||||
"PF7:EVENTOUT" : 15,
|
||||
"PF7:FSMC_NREG" : 12,
|
||||
"PF7:TIM11_CH1" : 3,
|
||||
"PF8:EVENTOUT" : 15,
|
||||
"PF8:FSMC_NIOWR" : 12,
|
||||
"PF8:TIM13_CH1" : 9,
|
||||
"PF9:EVENTOUT" : 15,
|
||||
"PF9:FSMC_CD" : 12,
|
||||
"PF9:TIM14_CH1" : 9,
|
||||
"PG0:EVENTOUT" : 15,
|
||||
"PG0:FSMC_A10" : 12,
|
||||
"PG10:EVENTOUT" : 15,
|
||||
"PG10:FSMC_NCE4_1" : 12,
|
||||
"PG10:FSMC_NE3" : 12,
|
||||
"PG11:ETH_MII_TX_EN" : 11,
|
||||
"PG11:ETH_RMII_TX_EN" : 11,
|
||||
"PG11:EVENTOUT" : 15,
|
||||
"PG11:FSMC_NCE4_2" : 12,
|
||||
"PG12:EVENTOUT" : 15,
|
||||
"PG12:FSMC_NE4" : 12,
|
||||
"PG12:USART6_RTS" : 8,
|
||||
"PG13:ETH_MII_TXD0" : 11,
|
||||
"PG13:ETH_RMII_TXD0" : 11,
|
||||
"PG13:EVENTOUT" : 15,
|
||||
"PG13:FSMC_A24" : 12,
|
||||
"PG13:UART6_CTS" : 8,
|
||||
"PG14:ETH_MII_TXD1" : 11,
|
||||
"PG14:ETH_RMII_TXD1" : 11,
|
||||
"PG14:EVENTOUT" : 15,
|
||||
"PG14:FSMC_A25" : 12,
|
||||
"PG14:USART6_TX" : 8,
|
||||
"PG1:EVENTOUT" : 15,
|
||||
"PG1:FSMC_A11" : 12,
|
||||
"PG2:EVENTOUT" : 15,
|
||||
"PG2:FSMC_A12" : 12,
|
||||
"PG3:EVENTOUT" : 15,
|
||||
"PG3:FSMC_A13" : 12,
|
||||
"PG4:EVENTOUT" : 15,
|
||||
"PG4:FSMC_A14" : 12,
|
||||
"PG5:EVENTOUT" : 15,
|
||||
"PG5:FSMC_A15" : 12,
|
||||
"PG6:EVENTOUT" : 15,
|
||||
"PG6:FSMC_INT2" : 12,
|
||||
"PG7:EVENTOUT" : 15,
|
||||
"PG7:FSMC_INT3" : 12,
|
||||
"PG7:USART6_CK" : 8,
|
||||
"PG8:ETH_PPS_OUT" : 11,
|
||||
"PG8:EVENTOUT" : 15,
|
||||
"PG8:USART6_RTS" : 8,
|
||||
"PG9:EVENTOUT" : 15,
|
||||
"PG9:FSMC_NCE3" : 12,
|
||||
"PG9:FSMC_NE2" : 12,
|
||||
"PG9:USART6_RX" : 8,
|
||||
"PH10:DCMI_D1" : 13,
|
||||
"PH10:EVENTOUT" : 15,
|
||||
"PH10:TIM5_CH1" : 2,
|
||||
"PH11:DCMI_D2" : 13,
|
||||
"PH11:EVENTOUT" : 15,
|
||||
"PH11:TIM5_CH2" : 2,
|
||||
"PH12:DCMI_D3" : 13,
|
||||
"PH12:EVENTOUT" : 15,
|
||||
"PH12:TIM5_CH3" : 2,
|
||||
"PH13:CAN1_TX" : 9,
|
||||
"PH13:EVENTOUT" : 15,
|
||||
"PH13:TIM8_CH1N" : 3,
|
||||
"PH14:DCMI_D4" : 13,
|
||||
"PH14:EVENTOUT" : 15,
|
||||
"PH14:TIM8_CH2N" : 3,
|
||||
"PH15:DCMI_D11" : 13,
|
||||
"PH15:EVENTOUT" : 15,
|
||||
"PH15:TIM8_CH3N" : 3,
|
||||
"PH1:EVENTOUT" : 15,
|
||||
"PH2:ETH_MII_CRS" : 11,
|
||||
"PH2:EVENTOUT" : 15,
|
||||
"PH3:ETH_MII_COL" : 11,
|
||||
"PH3:EVENTOUT" : 15,
|
||||
"PH4:EVENTOUT" : 15,
|
||||
"PH4:I2C2_SCL" : 4,
|
||||
"PH4:OTG_HS_ULPI_NXT" : 10,
|
||||
"PH5:EVENTOUT" : 15,
|
||||
"PH5:I2C2_SDA" : 4,
|
||||
"PH6:ETH_MII_RXD2" : 11,
|
||||
"PH6:EVENTOUT" : 15,
|
||||
"PH6:I2C2_SMBA" : 4,
|
||||
"PH6:TIM12_CH1" : 9,
|
||||
"PH7:ETH_MII_RXD3" : 11,
|
||||
"PH7:EVENTOUT" : 15,
|
||||
"PH7:I2C3_SCL" : 4,
|
||||
"PH8:DCMI_HSYNC" : 13,
|
||||
"PH8:EVENTOUT" : 15,
|
||||
"PH8:I2C3_SDA" : 4,
|
||||
"PH9:DCMI_D0" : 13,
|
||||
"PH9:EVENTOUT" : 15,
|
||||
"PH9:I2C3_SMBA" : 4,
|
||||
"PH9:TIM12_CH2" : 9,
|
||||
}
|
||||
ADC1_map = {
|
||||
# format is PIN : ADC1_CHAN
|
||||
# extracted from tabula-addfunc-F405.csv
|
||||
|
|
@ -982,3 +500,94 @@ ADC1_map = {
|
|||
"PC4" : 14,
|
||||
"PC5" : 15,
|
||||
}
|
||||
DMA_Map = {
|
||||
# format is [DMA_TABLE, StreamNum]
|
||||
# extracted from tabula-STM32F405-DMA.csvn
|
||||
"ADC1" : [(2,0),(2,4)],
|
||||
"ADC2" : [(2,2),(2,3)],
|
||||
"ADC3" : [(2,0),(2,1)],
|
||||
"CRYP_IN" : [(2,6)],
|
||||
"CRYP_OUT" : [(2,5)],
|
||||
"DAC1" : [(1,5)],
|
||||
"DAC2" : [(1,6)],
|
||||
"DCMI" : [(2,1),(2,7)],
|
||||
"HASH_IN" : [(2,7)],
|
||||
"I2C1_RX" : [(1,0),(1,5)],
|
||||
"I2C1_TX" : [(1,6),(1,7)],
|
||||
"I2C2_RX" : [(1,2),(1,3)],
|
||||
"I2C2_TX" : [(1,7)],
|
||||
"I2C3_RX" : [(1,2)],
|
||||
"I2C3_TX" : [(1,4)],
|
||||
"I2S2_EXT_RX" : [(1,3)],
|
||||
"I2S2_EXT_TX" : [(1,4)],
|
||||
"I2S3_EXT_RX" : [(1,2),(1,0)],
|
||||
"I2S3_EXT_TX" : [(1,5)],
|
||||
"SAI1_A" : [(2,1),(2,3)],
|
||||
"SAI1_B" : [(2,5),(2,4)],
|
||||
"SDIO" : [(2,3),(2,6)],
|
||||
"SPI1_RX" : [(2,0),(2,2)],
|
||||
"SPI1_TX" : [(2,3),(2,5)],
|
||||
"SPI2_RX" : [(1,3)],
|
||||
"SPI2_TX" : [(1,4)],
|
||||
"SPI3_RX" : [(1,0),(1,2)],
|
||||
"SPI3_TX" : [(1,5),(1,7)],
|
||||
"SPI4_RX" : [(2,0),(2,3)],
|
||||
"SPI4_TX" : [(2,1),(2,4)],
|
||||
"SPI5_RX" : [(2,3),(2,5)],
|
||||
"SPI5_TX" : [(2,4),(2,6)],
|
||||
"SPI6_RX" : [(2,6)],
|
||||
"SPI6_TX" : [(2,5)],
|
||||
"TIM1_CH1" : [(2,6),(2,1),(2,3)],
|
||||
"TIM1_CH2" : [(2,6),(2,2)],
|
||||
"TIM1_CH3" : [(2,6),(2,6)],
|
||||
"TIM1_CH4" : [(2,4)],
|
||||
"TIM1_COM" : [(2,4)],
|
||||
"TIM1_TRIG" : [(2,0),(2,4)],
|
||||
"TIM1_UP" : [(2,5)],
|
||||
"TIM2_CH1" : [(1,5)],
|
||||
"TIM2_CH2" : [(1,6)],
|
||||
"TIM2_CH3" : [(1,1)],
|
||||
"TIM2_CH4" : [(1,6),(1,7)],
|
||||
"TIM2_UP" : [(1,1),(1,7)],
|
||||
"TIM3_CH1" : [(1,4)],
|
||||
"TIM3_CH2" : [(1,5)],
|
||||
"TIM3_CH3" : [(1,7)],
|
||||
"TIM3_CH4" : [(1,2)],
|
||||
"TIM3_TRIG" : [(1,4)],
|
||||
"TIM3_UP" : [(1,2)],
|
||||
"TIM4_CH1" : [(1,0)],
|
||||
"TIM4_CH2" : [(1,3)],
|
||||
"TIM4_CH3" : [(1,7)],
|
||||
"TIM4_UP" : [(1,6)],
|
||||
"TIM5_CH1" : [(1,2)],
|
||||
"TIM5_CH2" : [(1,4)],
|
||||
"TIM5_CH3" : [(1,0)],
|
||||
"TIM5_CH4" : [(1,1),(1,3)],
|
||||
"TIM5_TRIG" : [(1,1),(1,3)],
|
||||
"TIM5_UP" : [(1,0),(1,6)],
|
||||
"TIM6_UP" : [(1,1)],
|
||||
"TIM7_UP" : [(1,2),(1,4)],
|
||||
"TIM8_CH1" : [(2,2),(2,2)],
|
||||
"TIM8_CH2" : [(2,2),(2,3)],
|
||||
"TIM8_CH3" : [(2,2),(2,4)],
|
||||
"TIM8_CH4" : [(2,7)],
|
||||
"TIM8_COM" : [(2,7)],
|
||||
"TIM8_TRIG" : [(2,7)],
|
||||
"TIM8_UP" : [(2,1)],
|
||||
"UART4_RX" : [(1,2)],
|
||||
"UART4_TX" : [(1,4)],
|
||||
"UART5_RX" : [(1,0)],
|
||||
"UART5_TX" : [(1,7)],
|
||||
"UART7_RX" : [(1,3)],
|
||||
"UART7_TX" : [(1,1)],
|
||||
"UART8_RX" : [(1,6)],
|
||||
"UART8_TX" : [(1,0)],
|
||||
"USART1_RX" : [(2,2),(2,5)],
|
||||
"USART1_TX" : [(2,7)],
|
||||
"USART2_RX" : [(1,5)],
|
||||
"USART2_TX" : [(1,6)],
|
||||
"USART3_RX" : [(1,1)],
|
||||
"USART3_TX" : [(1,3),(1,4)],
|
||||
"USART6_RX" : [(2,1),(2,2)],
|
||||
"USART6_TX" : [(2,6),(2,7)],
|
||||
}
|
||||
|
|
|
|||
|
|
@ -46,9 +46,9 @@ if len(sys.argv) != 2:
|
|||
|
||||
parse_dma_table(sys.argv[1], table)
|
||||
|
||||
sys.stdout.write("DMA_map = {\n");
|
||||
sys.stdout.write("DMA_Map = {\n");
|
||||
sys.stdout.write('\t# format is [DMA_TABLE, StreamNum]\n')
|
||||
sys.stdout.write('\t# extracted from %sn' % os.path.basename(sys.argv[1]))
|
||||
sys.stdout.write('\t# extracted from %sn\n' % os.path.basename(sys.argv[1]))
|
||||
|
||||
for k in sorted(table.iterkeys()):
|
||||
s = '"%s"' % k
|
||||
|
|
|
|||
Loading…
Reference in New Issue