mirror of https://github.com/ArduPilot/ardupilot
IOMCU: add application for ioboard firmware
This commit is contained in:
parent
17b61f72a3
commit
4608e90913
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//
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// Simple test for the AP_AHRS interface
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//
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#include <AP_HAL/AP_HAL.h>
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#include <AP_Math/AP_Math.h>
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#include <AP_Math/crc.h>
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#include "iofirmware.h"
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#include "hal.h"
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extern const AP_HAL::HAL &hal;
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#pragma GCC optimize("O0")
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#define PKT_MAX_REGS 32
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AP_IOMCU_FW iomcu;
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/*
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values for pkt.code
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*/
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enum iocode {
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// read types
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CODE_READ = 0,
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CODE_WRITE = 1,
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// reply codes
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CODE_SUCCESS = 0,
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CODE_CORRUPT = 1,
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CODE_ERROR = 2
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};
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// IO pages
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enum iopage {
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PAGE_CONFIG = 0,
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PAGE_STATUS = 1,
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PAGE_ACTUATORS = 2,
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PAGE_SERVOS = 3,
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PAGE_RAW_RCIN = 4,
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PAGE_RCIN = 5,
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PAGE_RAW_ADC = 6,
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PAGE_PWM_INFO = 7,
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PAGE_SETUP = 50,
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PAGE_DIRECT_PWM = 54,
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};
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// setup page registers
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#define PAGE_REG_SETUP_FEATURES 0
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#define P_SETUP_FEATURES_SBUS1_OUT 1
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#define P_SETUP_FEATURES_SBUS2_OUT 2
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#define P_SETUP_FEATURES_PWM_RSSI 4
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#define P_SETUP_FEATURES_ADC_RSSI 8
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#define P_SETUP_FEATURES_ONESHOT 16
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#define PAGE_REG_SETUP_ARMING 1
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#define P_SETUP_ARMING_IO_ARM_OK (1<<0)
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#define P_SETUP_ARMING_FMU_ARMED (1<<1)
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#define P_SETUP_ARMING_RC_HANDLING_DISABLED (1<<6)
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#define PAGE_REG_SETUP_PWM_RATE_MASK 2
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#define PAGE_REG_SETUP_DEFAULTRATE 3
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#define PAGE_REG_SETUP_ALTRATE 4
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#define PAGE_REG_SETUP_SBUS_RATE 19
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#define PAGE_REG_SETUP_HEATER_DUTY_CYCLE 21
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#define PAGE_REG_SETUP_FORCE_SAFETY_OFF 12
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#define PAGE_REG_SETUP_FORCE_SAFETY_ON 14
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#define FORCE_SAFETY_MAGIC 22027
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void setup();
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void loop();
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const AP_HAL::HAL& hal = AP_HAL::get_HAL();
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static uint32_t num_code_read = 0, num_bad_crc = 0, num_write_pkt = 0, num_unknown_pkt = 0;
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static uint32_t num_idle_rx = 0, num_dma_complete_rx = 0, num_total_rx = 0, num_rx_error = 0;
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void dma_rx_end_cb(UARTDriver *uart)
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{
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osalSysLockFromISR();
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uart->usart->CR3 &= ~(USART_CR3_DMAT | USART_CR3_DMAR);
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(void)uart->usart->SR;
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(void)uart->usart->DR;
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(void)uart->usart->DR;
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dmaStreamDisable(uart->dmarx);
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dmaStreamDisable(uart->dmatx);
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iomcu.process_io_packet();
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num_total_rx++;
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num_dma_complete_rx = num_total_rx - num_idle_rx;
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dmaStreamSetMemory0(uart->dmarx, &iomcu.rx_io_packet);
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dmaStreamSetTransactionSize(uart->dmarx, sizeof(iomcu.rx_io_packet));
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dmaStreamSetMode(uart->dmarx, uart->dmamode | STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
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dmaStreamEnable(uart->dmarx);
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uart->usart->CR3 |= USART_CR3_DMAR;
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dmaStreamSetMemory0(uart->dmatx, &iomcu.tx_io_packet);
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dmaStreamSetTransactionSize(uart->dmatx, iomcu.tx_io_packet.get_size());
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dmaStreamSetMode(uart->dmatx, uart->dmamode | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
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dmaStreamEnable(uart->dmatx);
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uart->usart->CR3 |= USART_CR3_DMAT;
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osalSysUnlockFromISR();
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}
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void idle_rx_handler(UARTDriver *uart) {
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volatile uint16_t sr = uart->usart->SR;
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if (sr & (USART_SR_ORE | /* overrun error - packet was too big for DMA or DMA was too slow */
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USART_SR_NE | /* noise error - we have lost a byte due to noise */
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USART_SR_FE)) { /* framing error - start/stop bit lost or line break */
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/* send a line break - this will abort transmission/reception on the other end */
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osalSysLockFromISR();
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uart->usart->CR1 |= USART_CR1_SBK;
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num_rx_error++;
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uart->usart->CR3 &= ~(USART_CR3_DMAT | USART_CR3_DMAR);
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(void)uart->usart->SR;
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(void)uart->usart->DR;
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(void)uart->usart->DR;
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dmaStreamDisable(uart->dmarx);
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dmaStreamDisable(uart->dmatx);
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dmaStreamSetMemory0(uart->dmarx, &iomcu.rx_io_packet);
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dmaStreamSetTransactionSize(uart->dmarx, sizeof(iomcu.rx_io_packet));
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dmaStreamSetMode(uart->dmarx, uart->dmamode | STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
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dmaStreamEnable(uart->dmarx);
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uart->usart->CR3 |= USART_CR3_DMAR;
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osalSysUnlockFromISR();
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return;
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}
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if(sr & USART_SR_IDLE) {
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dma_rx_end_cb(uart);
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num_idle_rx++;
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}
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}
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/*
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* UART driver configuration structure.
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*/
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static UARTConfig uart_cfg = {
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NULL,
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NULL,
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dma_rx_end_cb,
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NULL,
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NULL,
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idle_rx_handler,
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1500000, //1.5MBit
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USART_CR1_IDLEIE,
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0,
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0
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};
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void setup(void)
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{
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hal.gpio->init();
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hal.rcin->init();
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hal.rcout->init();
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for (uint8_t i = 0; i< 14; i++) {
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hal.rcout->enable_ch(i);
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}
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(void)uart_cfg;
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uartStart(&UARTD2, &uart_cfg);
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uartStartReceive(&UARTD2, sizeof(iomcu.rx_io_packet), &iomcu.rx_io_packet);
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}
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void loop(void)
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{
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iomcu.pwm_out_update();
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iomcu.heater_update();
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iomcu.rcin_update();
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}
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void AP_IOMCU_FW::pwm_out_update()
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{
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//TODO: PWM mixing
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memcpy(reg_servo.pwm, reg_direct_pwm.pwm, sizeof(reg_direct_pwm));
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for(uint8_t i = 0; i < SERVO_COUNT; i++) {
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if (reg_servo.pwm[i] != 0) {
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hal.rcout->write(i, reg_servo.pwm[i]);
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}
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}
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}
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void AP_IOMCU_FW::heater_update()
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{
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if (reg_setup.heater_duty_cycle == 0 || (AP_HAL::millis() - last_heater_ms > 3000UL)) {
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hal.gpio->write(0, 0);
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} else {
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uint8_t cycle = ((AP_HAL::millis() / 10UL) % 100U);
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hal.gpio->write(0, !(cycle >= reg_setup.heater_duty_cycle));
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}
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}
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void AP_IOMCU_FW::rcin_update()
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{
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if (hal.rcin->new_input()) {
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rc_input.count = hal.rcin->num_channels();
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rc_input.flags_rc_ok = true;
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for (uint8_t i = 0; i < IOMCU_MAX_CHANNELS; i++) {
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rc_input.pwm[i] = hal.rcin->read(i);
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}
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rc_input.last_input_us = AP_HAL::micros();
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}
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}
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void AP_IOMCU_FW::process_io_packet()
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{
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uint8_t rx_crc = rx_io_packet.crc;
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rx_io_packet.crc = 0;
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uint8_t calc_crc = crc_crc8((const uint8_t *)&rx_io_packet, rx_io_packet.get_size());
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if (rx_crc != calc_crc) {
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memset(&tx_io_packet, 0xFF, sizeof(tx_io_packet));
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tx_io_packet.count = 0;
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tx_io_packet.code = CODE_CORRUPT;
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tx_io_packet.crc = 0;
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tx_io_packet.crc = crc_crc8((const uint8_t *)&tx_io_packet, tx_io_packet.get_size());
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num_bad_crc++;
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return;
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}
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switch(rx_io_packet.code) {
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case CODE_READ:
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{
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num_code_read++;
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handle_code_read();
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}
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break;
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case CODE_WRITE:
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{
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num_write_pkt++;
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handle_code_write();
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}
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break;
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default:
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{
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num_unknown_pkt++;
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}
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break;
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}
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}
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bool AP_IOMCU_FW::handle_code_read()
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{
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uint16_t *values = NULL;
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#define COPY_PAGE(_page_name) \
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do { \
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values = (uint16_t *)&_page_name; \
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tx_io_packet.count = sizeof(_page_name) / sizeof(uint16_t); \
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} while(0);
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switch(rx_io_packet.page) {
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case PAGE_SETUP:
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COPY_PAGE(reg_setup);
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break;
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case PAGE_RAW_RCIN:
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COPY_PAGE(rc_input);
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break;
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case PAGE_STATUS:
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COPY_PAGE(reg_status);
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break;
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case PAGE_SERVOS:
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COPY_PAGE(reg_servo);
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break;
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default:
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return false;
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}
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last_page = rx_io_packet.page;
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last_offset = rx_io_packet.offset;
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/* if the offset is at or beyond the end of the page, we have no data */
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if (rx_io_packet.offset >= tx_io_packet.count) {
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return false;
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}
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/* correct the data pointer and count for the offset */
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values += rx_io_packet.offset;
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tx_io_packet.count -= rx_io_packet.offset;
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memcpy(tx_io_packet.regs, values, sizeof(uint16_t)*tx_io_packet.count);
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tx_io_packet.crc = 0;
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tx_io_packet.crc = crc_crc8((const uint8_t *)&tx_io_packet, tx_io_packet.get_size());
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return true;
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}
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bool AP_IOMCU_FW::handle_code_write()
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{
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switch(rx_io_packet.page) {
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case PAGE_SETUP:
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switch(rx_io_packet.offset) {
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case PAGE_REG_SETUP_ARMING:
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reg_setup.arming = rx_io_packet.regs[0];
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break;
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case PAGE_REG_SETUP_FORCE_SAFETY_OFF:
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if (rx_io_packet.regs[0] == FORCE_SAFETY_MAGIC) {
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reg_status.flag_safety_off = true;
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} else {
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return false;
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}
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break;
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case PAGE_REG_SETUP_FORCE_SAFETY_ON:
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if (rx_io_packet.regs[0] == FORCE_SAFETY_MAGIC) {
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reg_status.flag_safety_off = false;
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} else {
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return false;
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}
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break;
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case PAGE_REG_SETUP_ALTRATE:
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if (rx_io_packet.regs[0] < 25 && reg_setup.pwm_altclock == 1) {
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rx_io_packet.regs[0] = 25;
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}
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if (rx_io_packet.regs[0] > 400 && reg_setup.pwm_altclock == 1) {
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rx_io_packet.regs[0] = 400;
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}
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reg_setup.pwm_altrate = rx_io_packet.regs[0];
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hal.rcout->set_freq(reg_setup.pwm_rates, reg_setup.pwm_altrate);
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break;
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case PAGE_REG_SETUP_PWM_RATE_MASK:
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reg_setup.pwm_rates = rx_io_packet.regs[0];
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hal.rcout->set_freq(reg_setup.pwm_rates, reg_setup.pwm_altrate);
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break;
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case PAGE_REG_SETUP_DEFAULTRATE:
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if (rx_io_packet.regs[0] < 25 && reg_setup.pwm_altclock == 1) {
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rx_io_packet.regs[0] = 25;
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}
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if (rx_io_packet.regs[0] > 400 && reg_setup.pwm_altclock == 1) {
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rx_io_packet.regs[0] = 400;
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}
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reg_setup.pwm_defaultrate = rx_io_packet.regs[0];
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hal.rcout->set_default_rate(reg_setup.pwm_defaultrate);
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break;
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case PAGE_REG_SETUP_SBUS_RATE:
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break;
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case PAGE_REG_SETUP_FEATURES:
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reg_setup.features = rx_io_packet.regs[0];
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/* disable the conflicting options with SBUS 1 */
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if (reg_setup.features & (P_SETUP_FEATURES_SBUS1_OUT)) {
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reg_setup.features &= ~(P_SETUP_FEATURES_PWM_RSSI |
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P_SETUP_FEATURES_ADC_RSSI |
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P_SETUP_FEATURES_SBUS2_OUT);
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}
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break;
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case PAGE_REG_SETUP_HEATER_DUTY_CYCLE:
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reg_setup.heater_duty_cycle = rx_io_packet.regs[0];
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last_heater_ms = AP_HAL::millis();
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break;
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default:
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break;
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}
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break;
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case PAGE_DIRECT_PWM:
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{
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/* copy channel data */
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uint8_t i = 0, offset = rx_io_packet.offset, num_values = rx_io_packet.count;
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while ((offset < IOMCU_MAX_CHANNELS) && (num_values > 0)) {
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/* XXX range-check value? */
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if (rx_io_packet.regs[i] != PWM_IGNORE_THIS_CHANNEL) {
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reg_direct_pwm.pwm[offset] = rx_io_packet.regs[i];
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}
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offset++;
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num_values--;
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i++;
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}
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fmu_data_received_time = AP_HAL::millis();
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reg_status.flag_fmu_ok = true;
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reg_status.flag_raw_pwm = true;
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//TODO: Oneshot support
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break;
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}
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default:
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break;
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}
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memset(&tx_io_packet, 0xFF, sizeof(tx_io_packet));
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tx_io_packet.count = 0;
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tx_io_packet.code = CODE_SUCCESS;
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tx_io_packet.crc = 0;
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tx_io_packet.crc = crc_crc8((const uint8_t *)&tx_io_packet, tx_io_packet.get_size());
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return true;
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}
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AP_HAL_MAIN();
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@ -0,0 +1,130 @@
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#include <AP_HAL/AP_HAL.h>
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#include "ch.h"
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#define IOMCU_MAX_CHANNELS 16
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#define PKT_MAX_REGS 32
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#define PWM_IGNORE_THIS_CHANNEL UINT16_MAX
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#define SERVO_COUNT 8
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class AP_IOMCU_FW {
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public:
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void process_io_packet();
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struct PACKED IOPacket {
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uint8_t count:6;
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uint8_t code:2;
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uint8_t crc;
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uint8_t page;
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uint8_t offset;
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uint16_t regs[PKT_MAX_REGS];
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// get packet size in bytes
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uint8_t get_size(void) const {
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return count*2 + 4;
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}
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} rx_io_packet = {0}, tx_io_packet = {0};
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void pwm_out_update();
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void heater_update();
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void rcin_update();
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private:
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bool handle_code_write();
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bool handle_code_read();
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struct PACKED {
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/* default to RSSI ADC functionality */
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uint16_t features = 0;
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uint16_t arming = 0;
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uint16_t pwm_rates = 0;
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uint16_t pwm_defaultrate = 50;
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uint16_t pwm_altrate = 200;
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uint16_t sbus_rate = 72;
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uint16_t relays_pad = 0;
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uint16_t vbatt_scale = 10000;
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uint16_t set_debug = 0;
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uint16_t reboot_bl = 0;
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uint16_t crc[2] = {0};
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uint16_t rc_thr_failsafe_us;
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uint16_t pwm_reverse = 0;
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uint16_t trim_roll = 0;
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uint16_t trim_pitch = 0;
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uint16_t trim_yaw = 0;
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uint16_t ignore_safety = 0;
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uint16_t heater_duty_cycle = 0xFFFFU;
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uint16_t pwm_altclock = 1;
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} reg_setup;
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// PAGE_STATUS values
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struct PACKED {
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uint16_t freemem;
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uint16_t cpuload;
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// status flags
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uint16_t flag_outputs_armed:1;
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uint16_t flag_override:1;
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uint16_t flag_rc_ok:1;
|
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uint16_t flag_rc_ppm:1;
|
||||
uint16_t flag_rc_dsm:1;
|
||||
uint16_t flag_rc_sbus:1;
|
||||
uint16_t flag_fmu_ok:1;
|
||||
uint16_t flag_raw_pwm:1;
|
||||
uint16_t flag_mixer_ok:1;
|
||||
uint16_t flag_arm_sync:1;
|
||||
uint16_t flag_init_ok:1;
|
||||
uint16_t flag_failsafe:1;
|
||||
uint16_t flag_safety_off:1;
|
||||
uint16_t flag_fmu_initialised:1;
|
||||
uint16_t flag_rc_st24:1;
|
||||
uint16_t flag_rc_sumd_srxl:1;
|
||||
|
||||
uint16_t alarms;
|
||||
uint16_t vbatt;
|
||||
uint16_t ibatt;
|
||||
uint16_t vservo;
|
||||
uint16_t vrssi;
|
||||
uint16_t prssi;
|
||||
} reg_status = {0};
|
||||
|
||||
// PAGE_RAW_RCIN values
|
||||
struct PACKED {
|
||||
uint16_t count;
|
||||
uint16_t flags_frame_drop:1;
|
||||
uint16_t flags_failsafe:1;
|
||||
uint16_t flags_dsm11:1;
|
||||
uint16_t flags_mapping_ok:1;
|
||||
uint16_t flags_rc_ok:1;
|
||||
uint16_t flags_unused:11;
|
||||
uint16_t nrssi;
|
||||
uint16_t data;
|
||||
uint16_t frame_count;
|
||||
uint16_t lost_frame_count;
|
||||
uint16_t pwm[IOMCU_MAX_CHANNELS];
|
||||
uint16_t last_frame_count;
|
||||
uint32_t last_input_us;
|
||||
} rc_input = {0};
|
||||
|
||||
// PAGE_SERVO values
|
||||
struct {
|
||||
uint16_t pwm[IOMCU_MAX_CHANNELS] = {0};
|
||||
} reg_servo;
|
||||
|
||||
// PAGE_SERVO values
|
||||
struct {
|
||||
uint16_t pwm[IOMCU_MAX_CHANNELS]= {0};
|
||||
} reg_direct_pwm;
|
||||
|
||||
// output rates
|
||||
struct {
|
||||
uint16_t freq;
|
||||
uint16_t chmask;
|
||||
uint16_t default_freq = 50;
|
||||
uint16_t sbus_rate_hz;
|
||||
} rate;
|
||||
|
||||
uint8_t last_page;
|
||||
uint8_t last_offset;
|
||||
uint32_t fmu_data_received_time;
|
||||
uint32_t last_heater_ms;
|
||||
};
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
#!/usr/bin/env python
|
||||
# encoding: utf-8
|
||||
|
||||
def build(bld):
|
||||
bld.ap_stlib(
|
||||
name= 'iofirmware_libs',
|
||||
ap_vehicle='iofirmware',
|
||||
ap_libraries= [
|
||||
'AP_Buffer',
|
||||
'AP_Common',
|
||||
'AP_HAL',
|
||||
'AP_HAL_Empty',
|
||||
'AP_Math',
|
||||
'AP_RCProtocol',
|
||||
],
|
||||
exclude_src=[
|
||||
'libraries/AP_HAL_ChibiOS/Storage.cpp'
|
||||
]
|
||||
)
|
||||
bld.ap_program(
|
||||
program_name='iofirmware',
|
||||
use='iofirmware_libs',
|
||||
program_groups=['bin'],
|
||||
)
|
Loading…
Reference in New Issue