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AP_HAL_ChibiOS: update clock config for FDCAN and External Flash

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This commit is contained in:
Siddharth Purohit 2021-06-22 20:51:18 +05:30 committed by Andrew Tridgell
parent 35340bf7f2
commit 245f9d21b3
6 changed files with 3111 additions and 3087 deletions
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1232
libraries/AP_HAL_ChibiOS/hwdef/STM32CubeConf/H7-16MHz/H7-16MHz.ioc
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1229
libraries/AP_HAL_ChibiOS/hwdef/STM32CubeConf/H7-24MHz/H7-24MHz.ioc
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1229
libraries/AP_HAL_ChibiOS/hwdef/STM32CubeConf/H7-25MHz/H7-25MHz.ioc
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1229
libraries/AP_HAL_ChibiOS/hwdef/STM32CubeConf/H7-8MHz/H7-8MHz.ioc
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1231
libraries/AP_HAL_ChibiOS/hwdef/STM32CubeConf/H7-no-xtal/H7-no-xtal.ioc
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48
libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h
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@ -98,7 +98,7 @@
#define STM32_HSE_ENABLED FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_PLL1_DIVM_VALUE 4
#define STM32_PLL2_DIVM_VALUE 4
#define STM32_PLL2_DIVM_VALUE 8
#define STM32_PLL3_DIVM_VALUE 4
#define STM32_PLLSRC STM32_PLLSRC_HSI_CK
#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
@ -125,7 +125,7 @@
#define STM32_HSE_ENABLED TRUE
#define STM32_HSI_ENABLED FALSE
#define STM32_PLL1_DIVM_VALUE 3
#define STM32_PLL2_DIVM_VALUE 3
#define STM32_PLL2_DIVM_VALUE 2
#define STM32_PLL3_DIVM_VALUE 6
#elif STM32_HSECLK == 25000000U
@ -133,7 +133,7 @@
#define STM32_HSE_ENABLED TRUE
#define STM32_HSI_ENABLED FALSE
#define STM32_PLL1_DIVM_VALUE 2
#define STM32_PLL2_DIVM_VALUE 2
#define STM32_PLL2_DIVM_VALUE 5
#define STM32_PLL3_DIVM_VALUE 5
#else
#error "Unsupported HSE clock"
@ -146,27 +146,43 @@
#define STM32_PLL1_DIVQ_VALUE 8
#define STM32_PLL1_DIVR_VALUE 2
#define STM32_PLL2_DIVN_VALUE 16
#define STM32_PLL2_DIVP_VALUE 1
#define STM32_PLL2_DIVQ_VALUE 4
#define STM32_PLL2_DIVR_VALUE 2
#define STM32_PLL2_DIVN_VALUE 45
#define STM32_PLL2_DIVP_VALUE 2
#define STM32_PLL2_DIVQ_VALUE 5
#define STM32_PLL2_DIVR_VALUE 1
#define STM32_PLL3_DIVN_VALUE 15
#define STM32_PLL3_DIVP_VALUE 3
#define STM32_PLL3_DIVQ_VALUE 5
#define STM32_PLL3_DIVR_VALUE 8
#elif (STM32_HSECLK == 8000000U) || (STM32_HSECLK == 16000000U) || (STM32_HSECLK == 24000000U)
#elif (STM32_HSECLK == 8000000U) || (STM32_HSECLK == 16000000U)
// common clock tree for multiples of 8MHz crystals
#define STM32_PLL1_DIVN_VALUE 100
#define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 8
#define STM32_PLL1_DIVR_VALUE 2
#define STM32_PLL2_DIVN_VALUE 25
#define STM32_PLL2_DIVN_VALUE 45
#define STM32_PLL2_DIVP_VALUE 2
#define STM32_PLL2_DIVQ_VALUE 4
#define STM32_PLL2_DIVR_VALUE 4
#define STM32_PLL2_DIVQ_VALUE 5
#define STM32_PLL2_DIVR_VALUE 1
#define STM32_PLL3_DIVN_VALUE 72
#define STM32_PLL3_DIVP_VALUE 3
#define STM32_PLL3_DIVQ_VALUE 6
#define STM32_PLL3_DIVR_VALUE 9
#elif STM32_HSECLK == 24000000U
#define STM32_PLL1_DIVN_VALUE 100
#define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 8
#define STM32_PLL1_DIVR_VALUE 2
#define STM32_PLL2_DIVN_VALUE 30
#define STM32_PLL2_DIVP_VALUE 2
#define STM32_PLL2_DIVQ_VALUE 5
#define STM32_PLL2_DIVR_VALUE 1
#define STM32_PLL3_DIVN_VALUE 72
#define STM32_PLL3_DIVP_VALUE 3
@ -179,10 +195,10 @@
#define STM32_PLL1_DIVQ_VALUE 8
#define STM32_PLL1_DIVR_VALUE 2
#define STM32_PLL2_DIVN_VALUE 12
#define STM32_PLL2_DIVP_VALUE 1
#define STM32_PLL2_DIVQ_VALUE 2
#define STM32_PLL2_DIVR_VALUE 3
#define STM32_PLL2_DIVN_VALUE 72
#define STM32_PLL2_DIVP_VALUE 2
#define STM32_PLL2_DIVQ_VALUE 5
#define STM32_PLL2_DIVR_VALUE 1
#define STM32_PLL3_DIVN_VALUE 48
#define STM32_PLL3_DIVP_VALUE 3
@ -249,7 +265,7 @@
#ifndef STM32_CKPERSEL
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
#endif
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL2_R_CK
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
#define STM32_QSPISEL STM32_QSPISEL_HCLK
#define STM32_FMCSEL STM32_QSPISEL_HCLK
#define STM32_SWPSEL STM32_SWPSEL_PCLK1