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hwdef: fixes for BotBloxSwitch

This commit is contained in:
Andrew Tridgell 2024-07-10 16:41:05 +10:00 committed by Peter Barker
parent 14d94552eb
commit 23f628f26b
3 changed files with 57 additions and 24 deletions
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15
libraries/AP_HAL_ChibiOS/hwdef/BotBloxSwitch/defaults.parm Normal file
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@ -0,0 +1,15 @@
NET_ENABLE 1
NET_OPTIONS 1
# enable hw flow control
UART1_RTSCTS 1
# swap TX and RX
UART1_OPTIONS 8
SCR_ENABLE 1
SCR_VM_I_COUNT 1000000
SCR_HEAP_SIZE 150000
WEB_ENABLE 1
WEB_PORT 80

16
libraries/AP_HAL_ChibiOS/hwdef/BotBloxSwitch/hwdef-bl.dat
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@ -7,7 +7,7 @@
MCU STM32H7xx STM32H723xx
# crystal frequency
OSCILLATOR_HZ 0
OSCILLATOR_HZ 16000000
# setup build for a peripheral bootloader
env AP_PERIPH 1
@ -39,13 +39,18 @@ PA14 JTCK-SWCLK SWD
PD0 CAN1_RX CAN1
PD1 CAN1_TX CAN1
#PD4 USART2_DE USART2
PD5 USART2_TX USART2
PD6 USART2_RX USART2
PD8 USART3_TX USART3
PD9 USART3_RX USART3
PD12 USART3_RTS USART3
PD11 USART3_CTS USART3
# LEDs
PE5 LED_BOOTLOADER OUTPUT OPENDRAIN HIGH # blue
PC0 LED_STT1 OUTPUT OPENDRAIN HIGH
PA4 LED_STT2 OUTPUT OPENDRAIN HIGH
define HAL_LED_ON 0
define HAL_USE_EMPTY_STORAGE 1
@ -55,15 +60,14 @@ PC1 ETH_MDC ETH1
PA2 ETH_MDIO ETH1
PC4 ETH_RMII_RXD0 ETH1
PC5 ETH_RMII_RXD1 ETH1
#PB12 ETH_RMII_TXD0 ETH1
PG13 ETH_RMII_TXD0 ETH1
PB12 ETH_RMII_TXD0 ETH1
PB13 ETH_RMII_TXD1 ETH1
#PB11 ETH_RMII_TX_EN ETH1
PG11 ETH_RMII_TX_EN ETH1
PB11 ETH_RMII_TX_EN ETH1
PA7 ETH_RMII_CRS_DV ETH1
PA1 ETH_RMII_REF_CLK ETH1
define BOARD_PHY_ID MII_LAN8742A_ID
define BOARD_PHY_ADDRESS 0x0005
define BOARD_PHY_RMII
include ../include/network_bootloader.inc

50
libraries/AP_HAL_ChibiOS/hwdef/BotBloxSwitch/hwdef.dat
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@ -8,7 +8,7 @@ DEFAULTGPIO OUTPUT LOW PULLDOWN
MCU STM32H7xx STM32H723xx
# crystal frequency
OSCILLATOR_HZ 0
OSCILLATOR_HZ 16000000
# setup build for a peripheral bootloader
env AP_PERIPH 1
@ -42,46 +42,60 @@ PA9 VBUS INPUT OPENDRAIN
PD0 CAN1_RX CAN1
PD1 CAN1_TX CAN1
#PD4 USART2_DE USART2
PD5 USART2_TX USART2
PD6 USART2_RX USART2
PD8 USART3_TX USART3
PD9 USART3_RX USART3
PD12 USART3_RTS USART3
PD11 USART3_CTS USART3
# LEDs
PE3 LED_RED OUTPUT OPENDRAIN HIGH
PE4 LED_GREEN OUTPUT OPENDRAIN HIGH
PE5 LED_BLUE OUTPUT OPENDRAIN HIGH
PC0 LED_STT1 OUTPUT OPENDRAIN HIGH
PA4 LED_STT2 OUTPUT OPENDRAIN HIGH
define HAL_LED_ON 0
# use blue LED
define HAL_GPIO_PIN_LED HAL_GPIO_PIN_LED_BLUE
# use first LED
define HAL_GPIO_PIN_LED HAL_GPIO_PIN_LED_STT1
# Ethernet switch chip reset pin
PD13 GPIO_ETH_RST OUTPUT HIGH PULLUP
# CAN1 standby GPIO
PA0 GPIO_CAN_S OUTPUT LOW PULLUP
# GPIO/PWMs
#PC6 TIM3_CH1 TIM3 PWM(1) GPIO(100)
#PB14 TIM12_CH1 TIM12 PWM(2) GPIO(101)
#PB15 TIM12_CH2 TIM12 PWM(3) GPIO(102)
PC1 ETH_MDC ETH1
PA2 ETH_MDIO ETH1
PC4 ETH_RMII_RXD0 ETH1
PC5 ETH_RMII_RXD1 ETH1
#PB12 ETH_RMII_TXD0 ETH1
PG13 ETH_RMII_TXD0 ETH1
PB12 ETH_RMII_TXD0 ETH1
PB13 ETH_RMII_TXD1 ETH1
#PB11 ETH_RMII_TX_EN ETH1
PG11 ETH_RMII_TX_EN ETH1
PB11 ETH_RMII_TX_EN ETH1
PA7 ETH_RMII_CRS_DV ETH1
PA1 ETH_RMII_REF_CLK ETH1
define BOARD_PHY_ID MII_LAN8742A_ID
define BOARD_PHY_ADDRESS 0x0005
define BOARD_PHY_RMII
include ../include/network_PPPGW.inc
define HAL_PERIPH_ENABLE_NETWORKING
define AP_NETWORKING_MAX_INSTANCES 4
# allow load from USB
SERIAL_ORDER OTG1 USART3
# no ADC pins
define HAL_USE_ADC FALSE
define STM32_ADC_USE_ADC1 FALSE
define STM32_ADC_USE_ADC2 FALSE
define STM32_ADC_USE_ADC3 FALSE
define HAL_RCIN_THREAD_ENABLED 1
define HAL_SCHEDULER_LOOP_DELAY_ENABLED 1
define HAL_USE_ADC FALSE
define AP_SERIALMANAGER_REGISTER_ENABLED 1
define AP_SCRIPTING_ENABLED 1
define AP_FILESYSTEM_ROMFS_ENABLED 1
include ../include/network_PPPGW.inc