HAL_ChibiOS: disable interrupts during flash operations

we have now shown that interrupts being enabled during flash
operations can cause the infamous "68ms" bug, or watchdog when using a
32 bit timer on boards using flash for storage

The issue is quite repeatable with a load of a very large waypoint
file (over 500 waypoints) using "wp ftpload" in MAVProxy. This puts a
huge load on flash storage.

Our current working theory is that while doing flash writes for
storage on dual-bank we block access to only one bank, so if another
thread uses a timeout function with a short timeout while the flash
write is happening and chVTDoTickI calls code which crosses the flash
bank boundary then it can cause chVTDoTickI to violate the assumption
that no more than CH_CFG_ST_DELTA ticks pass while it is calculating
the value to set in the system timer. In that case we get a delay of a
full timer wrap, which is 68ms on boards with 16 bit timer and 70
minutes on boards with 32 bit timer

libraries/AP_HAL_ChibiOS/hwdef/common/flash.c

@@ -75,7 +75,7 @@
 
 // optionally disable interrupts during flash writes
 #ifndef STM32_FLASH_DISABLE_ISR
-#define STM32_FLASH_DISABLE_ISR 0
+#define STM32_FLASH_DISABLE_ISR 1
 #endif
 
 // the 2nd bank of flash needs to be handled differently