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AP_HAL: configure HAL_USE_QUADSPI and HAL_USE_OCTOSPI

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This commit is contained in:
Andy Piper 2022-08-17 20:26:58 +02:00 committed by Andrew Tridgell
parent edfb133375
commit 19bda7818c
3 changed files with 82 additions and 1 deletions
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7
libraries/AP_HAL/AP_HAL_Boards.h
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@ -313,6 +313,13 @@
#define HAL_CANFD_SUPPORTED 0 #define HAL_CANFD_SUPPORTED 0
#endif #endif
#ifndef HAL_USE_QUADSPI
#define HAL_USE_QUADSPI 0
#endif
#ifndef HAL_USE_OCTOSPI
#define HAL_USE_OCTOSPI 0
#endif
#ifndef __RAMFUNC__ #ifndef __RAMFUNC__
#define __RAMFUNC__ #define __RAMFUNC__
#endif #endif

53
libraries/AP_HAL/WSPIDevice.h
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@ -34,6 +34,7 @@ namespace AP_HAL
#if HAL_USE_WSPI_DEFAULT_CFG #if HAL_USE_WSPI_DEFAULT_CFG
namespace WSPI namespace WSPI
{ {
#if HAL_USE_QUADSPI
constexpr uint32_t CFG_CMD_MODE_MASK = (3LU << 8LU); constexpr uint32_t CFG_CMD_MODE_MASK = (3LU << 8LU);
constexpr uint32_t CFG_CMD_MODE_NONE = (0LU << 8LU); constexpr uint32_t CFG_CMD_MODE_NONE = (0LU << 8LU);
constexpr uint32_t CFG_CMD_MODE_ONE_LINE = (1LU << 8LU); constexpr uint32_t CFG_CMD_MODE_ONE_LINE = (1LU << 8LU);
@ -49,7 +50,6 @@ constexpr uint32_t CFG_ADDR_MODE_ONE_LINE = (1LU << 10LU);
constexpr uint32_t CFG_ADDR_MODE_TWO_LINES = (2LU << 10LU); constexpr uint32_t CFG_ADDR_MODE_TWO_LINES = (2LU << 10LU);
constexpr uint32_t CFG_ADDR_MODE_FOUR_LINES = (3LU << 10LU); constexpr uint32_t CFG_ADDR_MODE_FOUR_LINES = (3LU << 10LU);
constexpr uint32_t CFG_ADDR_SIZE_MASK = (3LU << 12LU); constexpr uint32_t CFG_ADDR_SIZE_MASK = (3LU << 12LU);
constexpr uint32_t CFG_ADDR_SIZE_8 = (0LU << 12LU); constexpr uint32_t CFG_ADDR_SIZE_8 = (0LU << 12LU);
constexpr uint32_t CFG_ADDR_SIZE_16 = (1LU << 12LU); constexpr uint32_t CFG_ADDR_SIZE_16 = (1LU << 12LU);
@ -79,6 +79,57 @@ constexpr uint32_t CFG_DATA_MODE_FOUR_LINES = (3LU << 24LU);
constexpr uint32_t CFG_DATA_DDR = (1LU << 31LU); constexpr uint32_t CFG_DATA_DDR = (1LU << 31LU);
constexpr uint32_t CFG_SIOO = (1LU << 28LU); constexpr uint32_t CFG_SIOO = (1LU << 28LU);
#else // OCTOSPI
constexpr uint32_t CFG_CMD_MODE_MASK = (7LU << 0LU);
constexpr uint32_t CFG_CMD_MODE_NONE = (0LU << 0LU);
constexpr uint32_t CFG_CMD_MODE_ONE_LINE = (1LU << 0LU);
constexpr uint32_t CFG_CMD_MODE_TWO_LINES = (2LU << 0LU);
constexpr uint32_t CFG_CMD_MODE_FOUR_LINES = (3LU << 0LU);
constexpr uint32_t CFG_CMD_MODE_EIGHT_LINES = (4LU << 0LU);
constexpr uint32_t CFG_CMD_SIZE_MASK = (3LU << 4LU);
constexpr uint32_t CFG_CMD_SIZE_8 = (0LU << 4LU);
constexpr uint32_t CFG_ADDR_MODE_MASK = (7LU << 8LU);
constexpr uint32_t CFG_ADDR_MODE_NONE = (0LU << 8LU);
constexpr uint32_t CFG_ADDR_MODE_ONE_LINE = (1LU << 8LU);
constexpr uint32_t CFG_ADDR_MODE_TWO_LINES = (2LU << 8LU);
constexpr uint32_t CFG_ADDR_MODE_FOUR_LINES = (3LU << 8LU);
constexpr uint32_t CFG_ADDR_MODE_EIGHT_LINES = (4LU << 8LU);
constexpr uint32_t CFG_ADDR_SIZE_MASK = (3LU << 12LU);
constexpr uint32_t CFG_ADDR_SIZE_8 = (0LU << 12LU);
constexpr uint32_t CFG_ADDR_SIZE_16 = (1LU << 12LU);
constexpr uint32_t CFG_ADDR_SIZE_24 = (2LU << 12LU);
constexpr uint32_t CFG_ADDR_SIZE_32 = (3LU << 12LU);
constexpr uint32_t CFG_ALT_MODE_MASK = (7LU << 16LU);
constexpr uint32_t CFG_ALT_MODE_NONE = (0LU << 16LU);
constexpr uint32_t CFG_ALT_MODE_ONE_LINE = (1LU << 16LU);
constexpr uint32_t CFG_ALT_MODE_TWO_LINES = (2LU << 16LU);
constexpr uint32_t CFG_ALT_MODE_FOUR_LINES = (3LU << 16LU);
constexpr uint32_t CFG_ALT_MODE_EIGHT_LINES = (4LU << 16LU);
constexpr uint32_t CFG_ALT_DDR = (1LU << 19LU);
constexpr uint32_t CFG_ALT_SIZE_MASK = (3LU << 20LU);
constexpr uint32_t CFG_ALT_SIZE_8 = (0LU << 20LU);
constexpr uint32_t CFG_ALT_SIZE_16 = (1LU << 20LU);
constexpr uint32_t CFG_ALT_SIZE_24 = (2LU << 20LU);
constexpr uint32_t CFG_ALT_SIZE_32 = (3LU << 20LU);
constexpr uint32_t CFG_DATA_MODE_MASK = (7LU << 24LU);
constexpr uint32_t CFG_DATA_MODE_NONE = (0LU << 24LU);
constexpr uint32_t CFG_DATA_MODE_ONE_LINE = (1LU << 24LU);
constexpr uint32_t CFG_DATA_MODE_TWO_LINES = (2LU << 24LU);
constexpr uint32_t CFG_DATA_MODE_FOUR_LINES = (3LU << 24LU);
constexpr uint32_t CFG_DATA_MODE_EIGHT_LINES= (4LU << 24LU);
constexpr uint32_t CFG_DATA_DDR = (1LU << 27LU);
constexpr uint32_t CFG_SIOO = (1LU << 31LU);
#endif // HAL_USE_QUADSPI
} }
#endif //#if HAL_USE_WSPI_DEFAULT_CFG #endif //#if HAL_USE_WSPI_DEFAULT_CFG

23
libraries/AP_HAL/board/chibios.h
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@ -120,3 +120,26 @@
#ifndef HAL_BOARD_STORAGE_DIRECTORY #ifndef HAL_BOARD_STORAGE_DIRECTORY
#define HAL_BOARD_STORAGE_DIRECTORY "/APM" #define HAL_BOARD_STORAGE_DIRECTORY "/APM"
#endif #endif
#if defined(STM32_WSPI_USE_QUADSPI1) && STM32_WSPI_USE_QUADSPI1
#define HAL_USE_QUADSPI1 TRUE
#else
#define HAL_USE_QUADSPI1 FALSE
#endif
#if defined(STM32_WSPI_USE_QUADSPI2) && STM32_WSPI_USE_QUADSPI2
#define HAL_USE_QUADSPI2 TRUE
#else
#define HAL_USE_QUADSPI2 FALSE
#endif
#if defined(STM32_WSPI_USE_OCTOSPI1) && STM32_WSPI_USE_OCTOSPI1
#define HAL_USE_OCTOSPI1 TRUE
#else
#define HAL_USE_OCTOSPI1 FALSE
#endif
#if defined(STM32_WSPI_USE_OCTOSPI2) && STM32_WSPI_USE_OCTOSPI2
#define HAL_USE_OCTOSPI2 TRUE
#else
#define HAL_USE_OCTOSPI2 FALSE
#endif
#define HAL_USE_QUADSPI (HAL_USE_QUADSPI1 || HAL_USE_QUADSPI2)
#define HAL_USE_OCTOSPI (HAL_USE_OCTOSPI1 || HAL_USE_OCTOSPI2)