From 17118977dc7a6f994880cfe8ca6fc70069f94c87 Mon Sep 17 00:00:00 2001
From: Andrew Tridgell <andrew@tridgell.net>
Date: Wed, 4 Dec 2019 10:29:52 +1100
Subject: [PATCH] HAL_ChibiOS: automatically set AP_FEATURE_RTSCTS

---
 libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py b/libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py
index 53dbbcebe5..fea9ff4e83 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py
+++ b/libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py
@@ -943,6 +943,7 @@ def write_UART_config(f):
     need_uart_driver = False
     OTG2_index = None
     devlist = []
+    have_rts_cts = False
     for dev in uart_list:
         if dev.startswith('UART'):
             n = int(dev[4:])
@@ -958,6 +959,7 @@ def write_UART_config(f):
         if dev + "_RTS" in bylabel:
             p = bylabel[dev + '_RTS']
             rts_line = 'PAL_LINE(GPIO%s,%uU)' % (p.port, p.pin)
+            have_rts_cts = True
         else:
             rts_line = "0"
         if dev.startswith('OTG2'):
@@ -985,6 +987,8 @@ def write_UART_config(f):
             f.write("%s, " % get_extra_bylabel(dev + "_RXINV", "POL", "0"))
             f.write("%d, " % get_gpio_bylabel(dev + "_TXINV"))
             f.write("%s}\n" % get_extra_bylabel(dev + "_TXINV", "POL", "0"))
+    if have_rts_cts:
+        f.write('#define AP_FEATURE_RTSCTS 1\n')
     if OTG2_index is not None:
         f.write('#define HAL_OTG2_UART_INDEX %d\n' % OTG2_index)
         f.write('''