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HAL_ChibiOS: fixed flash driver for F7

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we need a data sync barrier due to the F7 cache
This commit is contained in:
Andrew Tridgell 2018-06-16 10:54:14 +10:00
parent 82428dfbc6
commit 0cd46c063c
1 changed files with 5 additions and 0 deletions
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5
libraries/AP_HAL_ChibiOS/hwdef/common/flash.c
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@ -307,6 +307,8 @@ int32_t stm32_flash_write(uint32_t addr, const void *buf, uint32_t count)
// clear previous errors
FLASH->SR = 0xF3;
stm32_flash_wait_idle();
/* TODO: implement up_progmem_write() to support other sizes than 16-bits */
FLASH->CR &= ~(FLASH_CR_PSIZE);
FLASH->CR |= FLASH_CR_PSIZE_0 | FLASH_CR_PG;
@ -316,6 +318,9 @@ int32_t stm32_flash_write(uint32_t addr, const void *buf, uint32_t count)
putreg16(*hword, addr);
// ensure write ordering with cache
__DSB();
stm32_flash_wait_idle();
if (FLASH->SR) {