2018-05-29 03:07:36 -03:00
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# hw definition file for processing by chibios_hwdef.py
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# for FMUv3 hardware (ie. for CUAV-PixHack-v5 and Pixhawk4)
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2018-05-29 06:51:37 -03:00
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# MCU class and specific type. It is a F765, which is the same as F767
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# but without the TFT interface
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2018-05-29 03:07:36 -03:00
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MCU STM32F7xx STM32F767xx
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# crystal frequency
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OSCILLATOR_HZ 16000000
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define STM32_LSECLK 32768U
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define STM32_LSEDRV (3U << 3U)
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define STM32_PLLSRC STM32_PLLSRC_HSE
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define STM32_PLLM_VALUE 8
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define STM32_PLLN_VALUE 216
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define STM32_PLLP_VALUE 2
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define STM32_PLLQ_VALUE 9
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define CONFIG_HAL_BOARD_SUBTYPE HAL_BOARD_SUBTYPE_CHIBIOS_FMUV5
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# board ID for firmware load
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APJ_BOARD_ID 50
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FLASH_RESERVE_START_KB 32
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# board voltage
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STM32_VDD 330U
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# flash size
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FLASH_SIZE_KB 2048
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# order of UARTs (and USB)
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UART_ORDER OTG1
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# now we define the pins that USB is connected on
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PA11 OTG_FS_DM OTG1
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PA12 OTG_FS_DP OTG1
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# these are the pins for SWD debugging with a STlinkv2 or black-magic probe
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PA13 JTMS-SWDIO SWD
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PA14 JTCK-SWCLK SWD
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2018-05-29 06:51:37 -03:00
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# SPI1 - internal sensors
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PG11 SPI1_SCK SPI1
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PA6 SPI1_MISO SPI1
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PD7 SPI1_MOSI SPI1
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# SPI2 - FRAM
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PI1 SPI2_SCK SPI2
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PI2 SPI2_MISO SPI2
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PI3 SPI2_MOSI SPI2
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# SPI4 - sensors2
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PE2 SPI4_SCK SPI4
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PE13 SPI4_MISO SPI4
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PE6 SPI4_MOSI SPI4
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# SPI5 - external1
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PF7 SPI5_SCK SPI5
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PF8 SPI5_MISO SPI5
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PF9 SPI5_MOSI SPI5
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# SPI6 - external2
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PG13 SPI6_SCK SPI6
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PG12 SPI6_MISO SPI6
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PB5 SPI6_MOSI SPI6
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# sensor CS
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PF10 MS5611_CS CS
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PF2 ICM20689_CS CS
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PF3 ICM20602_CS CS
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PF4 BMI055_G_CS CS
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PG10 BMI055_A_CS CS
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PF5 FRAM_CS CS SPEED_VERYLOW
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# enable pins
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PE3 VDD_3V3_SENSORS_EN OUTPUT HIGH
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PF12 nVDD_5V_HIPOWER_EN OUTPUT LOW
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PG4 nVDD_5V_PERIPH_EN OUTPUT LOW
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PG5 VDD_5V_RC_EN OUTPUT HIGH
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PG6 VDD_5V_WIFI_EN OUTPUT HIGH
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PG7 VDD_3V3_SD_CARD_EN OUTPUT HIGH
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SPIDEV ms5611 SPI4 DEVID1 MS5611_CS MODE3 20*MHZ 20*MHZ
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SPIDEV mpu6000 SPI1 DEVID1 ICM20689_CS MODE3 1*MHZ 1*MHZ
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SPIDEV mpu60002 SPI1 DEVID2 ICM20602_CS MODE3 1*MHZ 1*MHZ
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SPIDEV bmi055_g SPI1 DEVID3 BMI055_G_CS MODE3 8*MHZ 8*MHZ
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SPIDEV bmi055_a SPI1 DEVID4 BMI055_A_CS MODE3 8*MHZ 8*MHZ
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SPIDEV ramtron SPI2 DEVID1 FRAM_CS MODE3 8*MHZ 8*MHZ
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# enable RAMTROM parameter storage
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2018-05-29 03:07:36 -03:00
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define HAL_STORAGE_SIZE 16384
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2018-05-29 06:51:37 -03:00
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define HAL_WITH_RAMTRON 1
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define STORAGE_FLASH_PAGE 7
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define HAL_BARO_DEFAULT HAL_BARO_MS5611_SPI
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define HAL_INS_DEFAULT HAL_INS_MPU60XX_SPI
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2018-05-29 03:07:36 -03:00
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define HAL_COMPASS_DEFAULT HAL_COMPASS_NONE
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define CH_DBG_ENABLE_ASSERTS TRUE
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define CH_DBG_ENABLE_CHECKS TRUE
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define CH_DBG_SYSTEM_STATE_CHECK TRUE
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define CH_DBG_ENABLE_STACK_CHECK TRUE
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2018-05-29 06:51:37 -03:00
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define HAL_SPI_CHECK_CLOCK_FREQ 1
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